Patents by Inventor Weng-Yi Chen
Weng-Yi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230406692Abstract: A microelectromechanical system (MEMS) microphone includes a substrate, a membrane supported relative to the substrate, an opening extending through the entire thickness of the membrane, and a spacer disposed on the sidewall of the opening. The spacer protrudes beyond the top surface of the membrane.Type: ApplicationFiled: August 2, 2022Publication date: December 21, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jung-Hao Chang, Weng-Yi Chen
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Patent number: 11345590Abstract: A semiconductor sensor, comprising a gas-sensing device and an integrated circuit is provided. The gas-sensing device includes a substrate having a sensing area and an interconnection area in the vicinity of the sensing area, an inter-metal dielectric (IMD) layer formed above the substrate in the sensing area and in the interconnection area, and an interconnect structure formed in the interconnection area; further includes a sensing electrode, a second TiO2-patterned portion, and a second Pt-patterned portion on the second TiO2-patterned portion in the sensing area. The interconnect structure includes a tungsten layer buried in the IMD layer, wherein part of a top surface of the tungsten layer is exposed by at least a via. The interconnect structure further includes a platinum layer formed in said at least the via, a TiO2 layer formed on the IMD layer, a first TiO2-patterned portion and a first Pt-patterned portion.Type: GrantFiled: November 13, 2020Date of Patent: May 31, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Fan Hu, Chia-Wei Lee, Chang-Sheng Hsu, Weng-Yi Chen
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Publication number: 20220119248Abstract: A micro electromechanical system (MEMS) includes a substrate, a semiconductor device and a protection wall. The substrate has a surface. The semiconductor device is disposed on the surface. The protection wall has a poly-silicon layer surrounding the semiconductor device and connecting to the surface.Type: ApplicationFiled: October 21, 2020Publication date: April 21, 2022Inventors: Jung-Hao CHANG, Weng-Yi CHEN
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Publication number: 20210061643Abstract: A semiconductor sensor, comprising a gas-sensing device and an integrated circuit is provided. The gas-sensing device includes a substrate having a sensing area and an interconnection area in the vicinity of the sensing area, an inter-metal dielectric (IMD) layer formed above the substrate in the sensing area and in the interconnection area, and an interconnect structure formed in the interconnection area; further includes a sensing electrode, a second TiO2-patterned portion, and a second Pt-patterned portion on the second TiO2-patterned portion in the sensing area. The interconnect structure includes a tungsten layer buried in the IMD layer, wherein part of a top surface of the tungsten layer is exposed by at least a via. The interconnect structure further includes a platinum layer formed in said at least the via, a TiO2 layer formed on the IMD layer, a first TiO2-patterned portion and a first Pt-patterned portion.Type: ApplicationFiled: November 13, 2020Publication date: March 4, 2021Inventors: Chih-Fan Hu, Chia-Wei Lee, Chang-Sheng Hsu, Weng-Yi Chen
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Patent number: 10870576Abstract: A semiconductor sensor, comprising a gas-sensing device and an integrated circuit is provided. The gas-sensing device includes a substrate having a sensing area and an interconnection area in the vicinity of the sensing area, an inter-metal dielectric (IMD) layer formed above the substrate in the sensing area and in the interconnection area, and an interconnect structure formed in the interconnection area; further includes a sensing electrode, a second TiO2-patterned portion, and a second Pt-patterned portion on the second TiO2-patterned portion in the sensing area. The interconnect structure includes a tungsten layer buried in the IMD layer, wherein part of a top surface of the tungsten layer is exposed by at least a via. The interconnect structure further includes a platinum layer formed in said at least the via, a TiO2 layer formed on the IMD layer, a first TiO2-patterned portion and a first Pt-patterned portion.Type: GrantFiled: March 19, 2020Date of Patent: December 22, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Fan Hu, Chia-Wei Lee, Chang-Sheng Hsu, Weng-Yi Chen
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Patent number: 10773953Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.Type: GrantFiled: September 7, 2017Date of Patent: September 15, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Meng-Jia Lin, Yung-Hsiao Lee, Weng-Yi Chen, Shih-Wei Li, Chung-Hsien Liu
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Patent number: 10737932Abstract: A MEMS structure includes a substrate, a dielectric layer, a membrane, a backplate, and a blocking layer. The substrate has a through-hole. The dielectric layer is disposed on the substrate and has a cavity in communication with the through-hole. The membrane has at least one vent hole, is embedded in the dielectric layer and together with the dielectric layer defines a first chamber that communicates with the through-hole. The backplate is disposed on the dielectric layer. One end of the blocking layer is embedded in the dielectric layer, and the other end of the blocking layer extends into the cavity; the blocking layer is spatially isolated from the membrane and at least partially overlaps with the at least one vent hole.Type: GrantFiled: February 25, 2019Date of Patent: August 11, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yuan-Sheng Lin, Jung-Hao Chang, Chang-Sheng Hsu, Weng-Yi Chen
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Publication number: 20200223687Abstract: A MEMS structure includes a substrate, a dielectric layer, a membrane, a backplate, and a blocking layer. The substrate has a through-hole. The dielectric layer is disposed on the substrate and has a cavity in communication with the through-hole. The membrane has at least one vent hole, is embedded in the dielectric layer and together with the dielectric layer defines a first chamber that communicates with the through-hole. The backplate is disposed on the dielectric layer. One end of the blocking layer is embedded in the dielectric layer, and the other end of the blocking layer extends into the cavity; the blocking layer is spatially isolated from the membrane and at least partially overlaps with the at least one vent hole.Type: ApplicationFiled: February 25, 2019Publication date: July 16, 2020Inventors: Yuan-Sheng LIN, Jung-Hao CHANG, Chang-Sheng HSU, Weng-Yi CHEN
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Publication number: 20200216304Abstract: A semiconductor sensor, comprising a gas-sensing device and an integrated circuit is provided. The gas-sensing device includes a substrate having a sensing area and an interconnection area in the vicinity of the sensing area, an inter-metal dielectric (IMD) layer formed above the substrate in the sensing area and in the interconnection area, and an interconnect structure formed in the interconnection area; further includes a sensing electrode, a second TiO2-patterned portion, and a second Pt-patterned portion on the second TiO2-patterned portion in the sensing area. The interconnect structure includes a tungsten layer buried in the IMD layer, wherein part of a top surface of the tungsten layer is exposed by at least a via. The interconnect structure further includes a platinum layer formed in said at least the via, a TiO2 layer formed on the IMD layer, a first TiO2-patterned portion and a first Pt-patterned portion.Type: ApplicationFiled: March 19, 2020Publication date: July 9, 2020Inventors: Chih-Fan Hu, Chia-Wei Lee, Chang-Sheng Hsu, Weng-Yi Chen
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Patent number: 10640368Abstract: A semiconductor sensor, comprising a gas-sensing device and an integrated circuit electrically connected to the gas-sensing device, is provided. The gas-sensing device includes a substrate having a sensing area and an interconnection area in the vicinity of the sensing area, an inter-metal dielectric (IMD) layer formed above the substrate in the sensing area and in the interconnection area, and an interconnect structure formed in the interconnection area. The interconnect structure includes a tungsten layer buried in the IMD layer, wherein part of a top surface of the tungsten layer is exposed by at least a via. The interconnect structure further includes a platinum layer formed in said at least the via, wherein the platinum (Pt) layer directly contacts the top surface of the tungsten layer.Type: GrantFiled: October 14, 2016Date of Patent: May 5, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Fan Hu, Chia-Wei Lee, Chang-Sheng Hsu, Weng-Yi Chen
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Patent number: 10475640Abstract: Provided herein is a method for manufacturing a semiconductor device. A substrate including a MEMS region and a connection region thereon is provided; a dielectric layer disposed on the substrate in the connection region is provided; a poly-silicon layer disposed on the dielectric layer is provided, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer is provided; and a passivation layer covering the dielectric layer is provided, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer, and a conductive layer conformally covering the connection pad and the poly-silicon layer in the transition region is provided.Type: GrantFiled: September 21, 2018Date of Patent: November 12, 2019Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Yan-Da Chen, Weng Yi Chen, Chang-Sheng Hsu, Kuan-Yu Wang, Yuan Sheng Lin
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Patent number: 10457546Abstract: A micro-electro-mechanical (MEMS) structure and a method for forming the same are disclosed. The MEMS structure includes a sacrificial layer, a lower dielectric film, an upper dielectric film, a plurality of through holes and a protective film. The sacrificial layer comprises an opening. The lower dielectric film is on the sacrificial layer. The upper dielectric film is on the lower dielectric film. The plurality of through holes passes through the lower dielectric film and the upper dielectric film. The protective film covers side walls of the upper dielectric film and the lower dielectric film and a film interface between the lower dielectric film and the upper dielectric film.Type: GrantFiled: March 14, 2018Date of Patent: October 29, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yuan-Sheng Lin, Weng-Yi Chen, Kuan-Yu Wang, Chih-Wei Liu
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Patent number: 10427935Abstract: A manufacturing method for a semiconductor structure is disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.Type: GrantFiled: September 21, 2018Date of Patent: October 1, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Te-Huang Chiu, Weng-Yi Chen, Kuan-Yu Wang
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Publication number: 20190027358Abstract: Provided herein is a method for manufacturing a semiconductor device. A substrate including a MEMS region and a connection region thereon is provided; a dielectric layer disposed on the substrate in the connection region is provided; a poly-silicon layer disposed on the dielectric layer is provided, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer is provided; and a passivation layer covering the dielectric layer is provided, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer, and a conductive layer conformally covering the connection pad and the poly-silicon layer in the transition region is provided.Type: ApplicationFiled: September 21, 2018Publication date: January 24, 2019Inventors: YAN-DA CHEN, WENG YI CHEN, CHANG-SHENG HSU, KUAN-YU WANG, YUAN SHENG LIN
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Publication number: 20190016591Abstract: A manufacturing method for a semiconductor structure is disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.Type: ApplicationFiled: September 21, 2018Publication date: January 17, 2019Inventors: Te-Huang Chiu, Weng-Yi Chen, Kuan-Yu Wang
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Publication number: 20180339901Abstract: A semiconductor process including the following steps is provided. A wafer is provided. The wafer has a front side and a back side. The wafer has a semiconductor device on the front side. A protection layer is formed on the front side of the wafer. The protection layer covers the semiconductor device. A material of the protection layer includes a photoresist material. A surface hardening treatment process is performed on the protection layer. A first patterning process is performed on the back side of the wafer. The semiconductor process can effectively protect the front side of the wafer during a backside process.Type: ApplicationFiled: July 7, 2017Publication date: November 29, 2018Applicant: United Microelectronics Corp.Inventors: Guo-Chih Wei, Weng-Yi Chen, Shih-Wei Li
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Patent number: 10112825Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.Type: GrantFiled: March 3, 2017Date of Patent: October 30, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Te-Huang Chiu, Weng-Yi Chen, Kuan-Yu Wang
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Patent number: 10115582Abstract: Provided herein is a semiconductor device is provided. The semiconductor device includes a substrate including a MEMS region and a connection region thereon; a dielectric layer disposed on the substrate in the connection region; a poly-silicon layer disposed on the dielectric layer, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer; and a passivation layer covering the dielectric layer, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer.Type: GrantFiled: June 5, 2015Date of Patent: October 30, 2018Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Yan-Da Chen, Weng Yi Chen, Chang-Sheng Hsu, Kuan-Yu Wang, Yuan Sheng Lin
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Publication number: 20180208460Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.Type: ApplicationFiled: March 3, 2017Publication date: July 26, 2018Inventors: Te-Huang Chiu, Weng-Yi Chen, Kuan-Yu Wang
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Publication number: 20180201498Abstract: A micro-electro-mechanical (MEMS) structure and a method for forming the same are disclosed. The MEMS structure includes a sacrificial layer, a lower dielectric film, an upper dielectric film, a plurality of through holes and a protective film. The sacrificial layer comprises an opening. The lower dielectric film is on the sacrificial layer. The upper dielectric film is on the lower dielectric film. The plurality of through holes passes through the lower dielectric film and the upper dielectric film. The protective film covers side walls of the upper dielectric film and the lower dielectric film and a film interface between the lower dielectric film and the upper dielectric film.Type: ApplicationFiled: March 14, 2018Publication date: July 19, 2018Inventors: Yuan-Sheng Lin, Weng-Yi Chen, Kuan-Yu Wang, Chih-Wei Liu