Patents by Inventor Wen-Sheng Chen
Wen-Sheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111178Abstract: A contact lens comprises an optical zone and a peripheral zone. The optical zone is used for vision correction. The peripheral zone surrounds the optical zone. The optical zone and the peripheral zone jointly define a geometric center and a horizontal axis passing through the geometric center. Two stabilization zones symmetrically arranged relative to the geometric center are formed in the peripheral zone. These stabilization zones gradually thicken relative to a base curved surface of the peripheral zone.Type: ApplicationFiled: September 19, 2023Publication date: April 4, 2024Inventors: Chih-Cheng CHEN, Hsien Sheng LIAO, Wen Chi YANG
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Publication number: 20240088842Abstract: Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Garming LIANG, Simon CHAI, Tzu-Jin YEH, En-Hsiang YEH, Wen-Sheng CHEN
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Patent number: 11921001Abstract: A method and system for inspecting deviation in dynamic characteristics of a feeding system are provided, and the method includes: exciting the feeding system and detecting vibrations of a subcomponent of a component to be inspected of the feeding system to generate a monitoring excitation signal in a monitoring mode; calculating, by a modal analysis method, monitoring eigenvalues and monitoring eigenvectors of the monitoring excitation signal; determining, by a modal verification method, similarity between the monitoring eigenvalues and standard eigenvalues of a digital twin model and similarity between the monitoring eigenvectors and standard eigenvectors of the digital twin model; determining that the dynamic characteristics of the subcomponent are deviated, when the monitoring eigenvalues and monitoring eigenvectors are not similar to the standard eigenvalues and standard eigenvectors. Therefore, the subcomponent whose dynamic characteristics are deviated can be sensed remotely and precisely.Type: GrantFiled: March 11, 2022Date of Patent: March 5, 2024Assignee: Hiwin Technologies Corp.Inventors: Hsien-Yu Chen, Yu-Sheng Chiu, Chih-Chun Cheng, Wen-Nan Cheng, Chi-Ming Liu
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Patent number: 11855590Abstract: Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.Type: GrantFiled: December 14, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Garming Liang, Simon Chai, Tzu-Jin Yeh, En-Hsiang Yeh, Wen-Sheng Chen
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Publication number: 20230125874Abstract: A power amplifier structure includes at least one power amplifier circuit. The power amplifier circuit includes a transistor of a first type connected in series with a transistor of a second type connected between the same voltage supply. In a non-limiting nonexclusive example, an n-type transistor is connected in series with a p-type transistor connected between Vdd. The power amplifier structure can include two amplifier circuits configured in a differential amplifier structure. The differential amplifier structure includes two amplifier circuits operably connected in parallel between the same voltage supply.Type: ApplicationFiled: March 15, 2022Publication date: April 27, 2023Inventors: Wen-Sheng Chen, En-Hsiang Yeh, Tzu-Jin Yeh
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Publication number: 20230127322Abstract: A semiconductor device includes: a polygonal inductive device disposed on a first layer on a substrate, the polygonal inductive device including a first line portion; a first conductive line disposed on a second layer on the substrate; a second conductive line disposed on a third layer on the substrate; and a first conductive via arranged to electrically couple the second conductive line to the first conductive line; wherein the first layer is different from the second layer and the third layer, the first conductive line is electrically connected to a reference voltage, and the first conductive line crosses the first line portion viewing from a top of the semiconductor device.Type: ApplicationFiled: December 21, 2022Publication date: April 27, 2023Inventors: WEN-SHENG CHEN, AN-HSUN LO, EN-HSIANG YEH, TZU-JIN YEH
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Publication number: 20230112936Abstract: Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.Type: ApplicationFiled: December 14, 2022Publication date: April 13, 2023Inventors: Garming LIANG, Simon CHAI, Tzu-Jin YEH, En-Hsiang YEH, Wen-Sheng CHEN
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Patent number: 11569164Abstract: A semiconductor device includes: a polygonal inductive device disposed on a first layer on a substrate, the polygonal inductive device including a first line portion; a first conductive line disposed on a second layer on the substrate; a second conductive line disposed on a third layer on the substrate; and a first conductive via arranged to electrically couple the second conductive line to the first conductive line; wherein the first layer is different from the second layer and the third layer, the first conductive line is electrically connected to a reference voltage, and the first conductive line crosses the first line portion viewing from a top of the semiconductor device.Type: GrantFiled: May 21, 2020Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wen-Sheng Chen, An-Hsun Lo, En-Hsiang Yeh, Tzu-Jin Yeh
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Patent number: 11558019Abstract: Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.Type: GrantFiled: November 4, 2019Date of Patent: January 17, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Garming Liang, Simon Chai, Tzu-Jin Yeh, En-Hsiang Yeh, Wen-Sheng Chen
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Publication number: 20220385251Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.Type: ApplicationFiled: August 8, 2022Publication date: December 1, 2022Inventors: An-Hsun LO, Wen-Sheng CHEN, En-Hsiang YEH, Tzu-Jin YEH
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Patent number: 11456711Abstract: The measurement method includes operations of applying a first gate bias voltage to a gate terminal of a first transistor that is included in a radio frequency (RF) power amplifier during a direct current (DC) measurement period, wherein the first transistor operates in a linear operation mode during the DC measurement period; measuring a first drain-source voltage of the first transistor and a current flowing through the first transistor via a connection node during the DC measurement period; applying a second gate bias voltage and a drain bias voltage to a gate terminal and a drain terminal of a second transistor that is electrically connected to the first transistor via the connection node; and measuring a DC value of the second transistor via the connection node during the DC measurement period.Type: GrantFiled: August 31, 2020Date of Patent: September 27, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: En-Hsiang Yeh, Wen-Sheng Chen, Chia-Ming Liang, Chung-Ho Chai, Zong-You Li, Tzu-Jin Yeh
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Patent number: 11456710Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.Type: GrantFiled: October 5, 2020Date of Patent: September 27, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: An-Hsun Lo, Wen-Sheng Chen, En-Hsiang Yeh, Tzu-Jin Yeh
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Publication number: 20220069779Abstract: The measurement method includes operations of applying a first gate bias voltage to a gate terminal of a first transistor that is included in a radio frequency (RF) power amplifier during a direct current (DC) measurement period, wherein the first transistor operates in a linear operation mode during the DC measurement period; measuring a first drain-source voltage of the first transistor and a current flowing through the first transistor via a connection node during the DC measurement period; applying a second gate bias voltage and a drain bias voltage to a gate terminal and a drain terminal of a second transistor that is electrically connected to the first transistor via the connection node; and measuring a DC value of the second transistor via the connection node during the DC measurement period.Type: ApplicationFiled: August 31, 2020Publication date: March 3, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: En-Hsiang Yeh, Wen-Sheng Chen, Chia-Ming Liang, Chung-Ho Chai, Zong-You Li, Tzu-Jin Yeh
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Patent number: 11244641Abstract: A device is applicable to a display driver, including a sampling circuit and a logic circuit. The sampling circuit is configured to sample a command signal by recording a plurality of command values of the command signal at different times. The plurality of command values corresponds to at least one data line of a pixel circuit. The logic circuit is electrically coupled to the sampling circuit, and is configured to receive the plurality of command values. The logic circuit is further configured to generate a filtered command signal according to the plurality of command values, and is configured to provide the filtered command signal to drive the pixel circuit.Type: GrantFiled: August 31, 2020Date of Patent: February 8, 2022Assignee: NOVATEK Microelectronics Corp.Inventors: Wei-Sheng Tseng, Wen-Sheng Chen
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Publication number: 20210118380Abstract: A device is applicable to a display driver, including a sampling circuit and a logic circuit. The sampling circuit is configured to sample a command signal by recording a plurality of command values of the command signal at different times. The plurality of command values corresponds to at least one data line of a pixel circuit. The logic circuit is electrically coupled to the sampling circuit, and is configured to receive the plurality of command values. The logic circuit is further configured to generate a filtered command signal according to the plurality of command values, and is configured to provide the filtered command signal to drive the pixel circuit.Type: ApplicationFiled: August 31, 2020Publication date: April 22, 2021Inventors: Wei-Sheng TSENG, Wen-Sheng CHEN
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Patent number: 10985618Abstract: A wireless transmitter includes a an amplifier; and a switchable transformer, coupled to the amplifier, wherein the amplifier is configured to be coupled to the switchable transformer in first and second configurations, wherein the first configuration causes the amplifier to provide a first output impedance to the switchable transformer, and wherein the second configuration causes the amplifier to provide a second output impedance to the switchable transformer, the first and second output impedances being different from each other.Type: GrantFiled: October 28, 2019Date of Patent: April 20, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Sheng Chen, An-Hsun Lo, En-Hsiang Yeh, Tzu-Jin Yeh
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Publication number: 20210021240Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.Type: ApplicationFiled: October 5, 2020Publication date: January 21, 2021Inventors: An-Hsun LO, Wen-Sheng Chen, En-Hsiang Yeh, Tzu-Jin Yeh
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Patent number: 10797655Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.Type: GrantFiled: November 4, 2016Date of Patent: October 6, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: An-Hsun Lo, Wen-Sheng Chen, En-Hsiang Yeh, Tzu-Jin Yeh
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Publication number: 20200279808Abstract: A semiconductor device includes: a polygonal inductive device disposed on a first layer on a substrate, the polygonal inductive device including a first line portion; a first conductive line disposed on a second layer on the substrate; a second conductive line disposed on a third layer on the substrate; and a first conductive via arranged to electrically couple the second conductive line to the first conductive line; wherein the first layer is different from the second layer and the third layer, the first conductive line is electrically connected to a reference voltage, and the first conductive line crosses the first line portion viewing from a top of the semiconductor device.Type: ApplicationFiled: May 21, 2020Publication date: September 3, 2020Inventors: WEN-SHENG CHEN, AN-HSUN LO, EN-HSIANG YEH, TZU-JIN YEH
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Patent number: 10672704Abstract: A semiconductor device includes: a polygonal inductive device disposed on a first layer on a substrate, the polygonal inductive device including a first line portion; a first conductive line disposed on a second layer on the substrate; a second conductive line disposed on a third layer on the substrate; and a first conductive via arranged to electrically couple the second conductive line to the first conductive line; wherein the first layer is different from the second layer and the third layer, the first conductive line is electrically connected to a reference voltage, and the first conductive line crosses the first line portion viewing from a top of the semiconductor device.Type: GrantFiled: April 27, 2018Date of Patent: June 2, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wen-Sheng Chen, An-Hsun Lo, En-Hsiang Yeh, Tzu-Jin Yeh