Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.

Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.

Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.

Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

Abstract: The present disclosure provides a control circuit of a memory array. The control circuit includes a first switch and a set termination circuit. The first switch is connected between a first voltage source and a data line of a resistive memory cell of the memory array. The set termination circuit has a first terminal connected to a control terminal of the first switch and a second terminal connected to the data line of the resistive memory cell of the memory array. When a data line voltage of the data line decreases to be lower than a first voltage in a first duration of the resistive memory cell performing a set operation, the set termination circuit turns off the first switch to terminate the set operation by stopping providing the first voltage of the first voltage source to the data line.

Abstract: The present disclosure provides a control circuit of a memory array. The control circuit includes a first switch and a set termination circuit. The first switch is connected between a first voltage source and a data line of a resistive memory cell of the memory array. The set termination circuit has a first terminal connected to a control terminal of the first switch and a second terminal connected to the data line of the resistive memory cell of the memory array. When a data line voltage of the data line decreases to be lower than a first voltage in a first duration of the resistive memory cell performing a set operation, the set termination circuit turns off the first switch to terminate the set operation by stopping providing the first voltage of the first voltage source to the data line.

Abstract: The present disclosure provides a control circuit of a memory array. The control circuit includes a first switch and a set termination circuit. The first switch is connected between a first voltage source and a data line of a resistive memory cell of the memory array. The set termination circuit has a first terminal connected to a control terminal of the first switch and a second terminal connected to the data line of the resistive memory cell of the memory array. When a data line voltage of the data line decreases to be lower than a first voltage in a first duration of the resistive memory cell performing a set operation, the set termination circuit turns off the first switch to terminate the set operation by stopping providing the first voltage of the first voltage source to the data line.

Abstract: The present disclosure provides a control circuit of a memory array. The control circuit includes a first switch and a set termination circuit. The first switch is connected between a first voltage source and a data line of a resistive memory cell of the memory array. The set termination circuit has a first terminal connected to a control terminal of the first switch and a second terminal connected to the data line of the resistive memory cell of the memory array. When a data line voltage of the data line decreases to be lower than a first voltage in a first duration of the resistive memory cell performing a set operation, the set termination circuit turns off the first switch to terminate the set operation by stopping providing the first voltage of the first voltage source to the data line.

Abstract: The present disclosure provides a control circuit of a memory array. The control circuit includes a first switch and a set termination circuit. The first switch is connected between a first voltage source and a data line of a resistive memory cell of the memory array. The set termination circuit has a first terminal connected to a control terminal of the first switch and a second terminal connected to the data line of the resistive memory cell of the memory array. When a data line voltage of the data line decreases to be lower than a first voltage in a first duration of the resistive memory cell performing a set operation, the set termination circuit turns off the first switch to terminate the set operation by stopping providing the first voltage of the first voltage source to the data line.

Abstract: The present disclosure provides a control circuit of a memory array. The control circuit includes a first switch and a set termination circuit. The first switch is connected between a first voltage source and a data line of a resistive memory cell of the memory array. The set termination circuit has a first terminal connected to a control terminal of the first switch and a second terminal connected to the data line of the resistive memory cell of the memory array. When a data line voltage of the data line decreases to be lower than a first voltage in a first duration of the resistive memory cell performing a set operation, the set termination circuit turns off the first switch to terminate the set operation by stopping providing the first voltage of the first voltage source to the data line.

Abstract: A receptacle connector (100) includes an insulative housing (1), a number of contacts (2) retained in the insulative housing, a metal shield (3) covering the insulative housing, a metal plate (4) assembled to the metal shield along a vertical direction perpendicular to the mating direction, and an insulative cover (5) fully molded over the metal shield and partly molded over the metal plate. The metal plate defines a pair of closed slits (412) behind a rear face of the insulative housing. The insulative cover terminates at the closed slits in a mating direction along which a mating plug connector is inserted.

Abstract: A receptacle connector (100) includes an insluative housing (1), a number of contacts (2) retained in the insulative housing; a metal shield (4) covering the insulative housing for defining a space for receiving a plug connector along an insertion direction, and a cable (3) having a first end soldered to a mother board of an electronic appliance and a second end directly soldered with the soldering portions of the contacts in a first embodiment and indirectly connected with the contacts via a printed circuit board in a second embodiment.

Abstract: A waterproof electrical connector (100) includes a number of terminals (2), a metallic shell (1), and an insulating housing (3) molded outside of the metal shell (1) to thereby define a passageway (10). The insulating housing (1) includes a base portion (33) and a tongue portion (31) extending forwardly from the base portion (33). The base portion (33) includes at least one mold cavity (331) for inserting a mold. The mold cavity (331) and the passageway (10) are spaced apart from each other along the insertion/extraction direction for having better waterproof function.

Abstract: A receptacle connector (100) includes an insulative housing (1), a number of contacts (2) retained in the insulative housing, a metal shield (3) covering the insulative housing, a metal plate (4) assembled to the metal shield along a vertical direction perpendicular to the mating direction, and an insulative cover (5) fully molded over the metal shield and partly molded over the metal plate. The metal plate defines a pair of closed slits (412) behind a rear face of the insulative housing. The insulative cover terminates at the closed slits in a mating direction along which a mating plug connector is inserted.

Abstract: A receptacle connector (100) includes an insluative housing (1), a number of contacts (2) retained in the insulative housing; a metal shield (4) covering the insulative housing for defining a space for receiving a plug connector along an insertion direction, and a cable (3) having a first end soldered to a mother board of an electronic appliance and a second end directly soldered with the soldering portions of the contacts in a first embodiment and indirectly connected with the contacts via a printed circuit board in a second embodiment.

Abstract: A waterproof electrical connector (100) includes a number of terminals (2), a metallic shell (1), and an insulating housing (3) molded outside of the metal shell (1) to thereby define a passageway (10). The insulating housing (1) includes a base portion (33) and a tongue portion (31) extending forwardly from the base portion (33). The base portion (33) includes at least one mold cavity (331) for inserting a mold. The mold cavity (331) and the passageway (10) are spaced apart from each other along the insertion/extraction direction for having better waterproof function.