Patents by Inventor Weon-Hong Kim

Weon-Hong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10312341
    Abstract: An integrated circuit device includes a first gate stack formed on a first high dielectric layer and comprising a first work function adjustment metal containing structure and a second gate stack formed on a second high dielectric layer and comprising a second work function adjustment metal containing structure having an oxygen content that is greater than that of the first work function adjustment metal containing structure.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: June 4, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-jin Lim, Gi-gwan Park, Weon-hong Kim
  • Publication number: 20180090585
    Abstract: An integrated circuit device includes a first gate stack formed on a first high dielectric layer and comprising a first work function adjustment metal containing structure and a second gate stack formed on a second high dielectric layer and comprising a second work function adjustment metal containing structure having an oxygen content that is greater than that of the first work function adjustment metal containing structure.
    Type: Application
    Filed: November 28, 2017
    Publication date: March 29, 2018
    Inventors: Ha-jin LIM, Gi-gwan PARK, Weon-hong KIM
  • Patent number: 9922879
    Abstract: An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode covering the gate insulation layer and a hydrogen atomic layer disposed along an interface between the fin-shaped active region and the gate insulation layer. A method of manufacturing the integrated circuit device may include forming an insulating layer covering a lower portion of a preliminary fin-shaped active region, forming a fin-shaped active region having an outer surface with an increased smoothness through annealing an upper portion of the preliminary fin-shaped active region in a hydrogen atmosphere and forming a hydrogen atomic layer covering the outer surface of the fin-shaped active region. A gate insulation layer and a gate electrode may be formed to cover a top surface and opposite sidewalls of the fin-shaped active region.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: March 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Weon-hong Kim, Dong-su Yoo, Min-joo Lee, Moon-kyun Song, Soo-jung Choi
  • Patent number: 9859392
    Abstract: An integrated circuit device includes a first gate stack formed on a first high dielectric layer and comprising a first work function adjustment metal containing structure and a second gate stack formed on a second high dielectric layer and comprising a second work function adjustment metal containing structure having an oxygen content that is greater than that of the first work function adjustment metal containing structure.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: January 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-jin Lim, Gi-gwan Park, Weon-hong Kim
  • Publication number: 20170372971
    Abstract: An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode covering the gate insulation layer and a hydrogen atomic layer disposed along an interface between the fin-shaped active region and the gate insulation layer. A method of manufacturing the integrated circuit device may include forming an insulating layer covering a lower portion of a preliminary fin-shaped active region, forming a fin-shaped active region having an outer surface with an increased smoothness through annealing an upper portion of the preliminary fin-shaped active region in a hydrogen atmosphere and forming a hydrogen atomic layer covering the outer surface of the fin-shaped active region. A gate insulation layer and a gate electrode may be formed to cover a top surface and opposite sidewalls of the fin-shaped active region.
    Type: Application
    Filed: September 8, 2017
    Publication date: December 28, 2017
    Inventors: Weon-hong KIM, Dong-su YOO, Min-joo LEE, Moon-kyun SONG, Soo-jung CHOI
  • Patent number: 9779996
    Abstract: An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode covering the gate insulation layer and a hydrogen atomic layer disposed along an interface between the fin-shaped active region and the gate insulation layer. A method of manufacturing the integrated circuit device may include forming an insulating layer covering a lower portion of a preliminary fin-shaped active region, forming a fin-shaped active region having an outer surface with an increased smoothness through annealing an upper portion of the preliminary fin-shaped active region in a hydrogen atmosphere and forming a hydrogen atomic layer covering the outer surface of the fin-shaped active region. A gate insulation layer and a gate electrode may be formed to cover a top surface and opposite sidewalls of the fin-shaped active region.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: October 3, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Weon-hong Kim, Dong-su Yoo, Min-Joo Lee, Moon-Kyun Song, Soo-jung Choi
  • Patent number: 9702041
    Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: July 11, 2017
    Assignees: SAMSUNG ELECTRONICS CO., LTD., GENITECH, INC.
    Inventors: Seok-jun Won, Yong-min Yoo, Dae-youn Kim, Young-hoon Kim, Dae-jin Kwon, Weon-hong Kim
  • Patent number: 9698021
    Abstract: In a method of forming a layer, a substrate is loaded into a chamber and placed at a home position that is a first relative angular position. A process cycle is performed a number of times while the substrate is at the home position. The cycle includes directing source gas onto the substrate at a first location adjacent the periphery of the substrate, purging the chamber, directing reaction gas onto the substrate from the first location, and purging the chamber. The cycle is performed another number of times while the substrate is at another relative angular position, i.e., at a position rotated about its general center relative from the home position.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: July 4, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Joo Lee, Weon-Hong Kim, Moon-Kyun Song, Dong-Su Yoo, Soo-Jung Choi
  • Publication number: 20170084711
    Abstract: An integrated circuit device includes a first gate stack formed on a first high dielectric layer and comprising a first work function adjustment metal containing structure and a second gate stack formed on a second high dielectric layer and comprising a second work function adjustment metal containing structure having an oxygen content that is greater than that of the first work function adjustment metal containing structure.
    Type: Application
    Filed: September 19, 2016
    Publication date: March 23, 2017
    Inventors: Ha-jin LIM, Gi-gwan PARK, Weon-hong KIM
  • Patent number: 9583592
    Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed on a substrate. A first spacer layer is formed on the substrate to cover the dummy gate structure. A nitridation process is performed on the first spacer layer. An upper portion of the substrate adjacent to the dummy gate structure is removed to form a trench. An inner wall of the trench is cleaned. An epitaxial layer is formed to fill the trench. The dummy gate structure is replaced with a gate structure.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: February 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pan-Kwi Park, Dong-Suk Shin, Seok-Jun Won, Weon-Hong Kim, Jae-Gon Lee
  • Publication number: 20170033013
    Abstract: An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode covering the gate insulation layer and a hydrogen atomic layer disposed along an interface between the fin-shaped active region and the gate insulation layer. A method of manufacturing the integrated circuit device may include forming an insulating layer covering a lower portion of a preliminary fin-shaped active region, forming a fin-shaped active region having an outer surface with an increased smoothness through annealing an upper portion of the preliminary fin-shaped active region in a hydrogen atmosphere and forming a hydrogen atomic layer covering the outer surface of the fin-shaped active region. A gate insulation layer and a gate electrode may be formed to cover a top surface and opposite sidewalls of the fin-shaped active region.
    Type: Application
    Filed: May 12, 2016
    Publication date: February 2, 2017
    Inventors: Weon-hong Kim, Dong-su Yoo, Min-Joo Lee, Moon-Kyun Song, Soo-jung Choi
  • Publication number: 20160281234
    Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.
    Type: Application
    Filed: June 8, 2016
    Publication date: September 29, 2016
    Applicants: SAMSUNG ELECTRONICS CO., LTD., GENITECH, INC.
    Inventors: Seok-jun WON, Yong-min YOO, Dae-youn KIM, Young-hoon KIM, Dae-jin KWON, Weon-hong KIM
  • Patent number: 9431515
    Abstract: Methods of forming semiconductor devices are provided. A method of forming a semiconductor device includes forming an insulating layer that includes a trench therein. The method includes forming a high-k layer in the trench. Moreover, the method includes forming a metal layer on the high-k layer, then performing a first heat treatment at a first temperature, and performing a second heat treatment at a second temperature that is higher than the first temperature.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: August 30, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Jun Won, Weon-Hong Kim, Moon-Kyun Song
  • Patent number: 9406502
    Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: August 2, 2016
    Assignees: SAMSUNG ELECTRONICS CO., LTD., GENITECH, INC.
    Inventors: Seok-jun Won, Yong-min Yoo, Dae-youn Kim, Young-hoon Kim, Dae-jin Kwon, Weon-hong Kim
  • Publication number: 20160189951
    Abstract: In a method of forming a layer, a substrate is loaded into a chamber and placed at a home position that is a first relative angular position. A process cycle is performed a number of times while the substrate is at the home position. The cycle includes directing source gas onto the substrate at a first location adjacent the periphery of the substrate, purging the chamber, directing reaction gas onto the substrate from the first location, and purging the chamber. The cycle is performed another number of times while the substrate is at another relative angular position, i.e., at a position rotated about its general center relative from the home position.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 30, 2016
    Inventors: MIN-JOO LEE, WEON-HONG KIM, MOON-KYUN SONG, DONG-SU YOO, SOO-JUNG CHOI
  • Patent number: 9318335
    Abstract: A method of fabricating a semiconductor device includes forming an interface layer on a substrate, forming a first gate insulating layer having a first dielectric constant on the interface layer, forming a second gate insulating layer having a second dielectric constant smaller than the first dielectric constant on the first gate insulating layer, annealing the substrate, nitriding a resultant of the annealed first and second gate insulating layers to form a nitrided gate insulator, forming a work function control layer on the nitride gate insulator, and forming a metal gate electrode on the work function control layer. At least one of the work function control layer and the metal gate electrode is of or includes aluminum (Al).
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: April 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Weon-Hong Kim, Moon-Kyun Song, Min-Joo Lee, Hyung-Suk Jung
  • Publication number: 20160064225
    Abstract: A method of fabricating a semiconductor device includes forming an interface layer on a substrate, forming a first gate insulating layer having a first dielectric constant on the interface layer, forming a second gate insulating layer having a second dielectric constant smaller than the first dielectric constant on the first gate insulating layer, annealing the substrate, nitriding a resultant of the annealed first and second gate insulating layers to form a nitrided gate insulator, forming a work function control layer on the nitride gate insulator, and forming a metal gate electrode on the work function control layer. At least one of the work function control layer and the metal gate electrode is of or includes aluminum (Al).
    Type: Application
    Filed: April 14, 2015
    Publication date: March 3, 2016
    Inventors: WEON-HONG KIM, MOON-KYUN SONG, MIN-JOO LEE, HYUNG-SUK JUNG
  • Patent number: 9275993
    Abstract: A semiconductor device includes a first interface film on a first area of a substrate, the first interface film including a first growth interface film and a second growth interface film on a lower portion of the first growth interface film, a first dielectric film on the first interface film, and a first gate electrode on the first dielectric film.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: March 1, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Weon-Hong Kim, Moon-Kyun Song, Seok-Jun Won
  • Publication number: 20160049478
    Abstract: A method for fabricating a semiconductor device comprises forming a gate insulation layer on a substrate including a first region and a second region, forming a first gate conductive layer and a capping layer on the first region and the second region and heat-treating the substrate, removing the capping layer from the first region and the second region, forming a second gate conductive layer on the first region and the second region, nitriding the second gate conductive layer, and forming a third gate conductive layer on the second region.
    Type: Application
    Filed: April 3, 2015
    Publication date: February 18, 2016
    Inventors: Moon-Kyun Song, Weon-Hong Kim, Soo-Jung Choi, Yoon-Tae Hwang
  • Publication number: 20160035861
    Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed on a substrate. A first spacer layer is formed on the substrate to cover the dummy gate structure. A nitridation process is performed on the first spacer layer. An upper portion of the substrate adjacent to the dummy gate structure is removed to form a trench. An inner wall of the trench is cleaned. An epitaxial layer is formed to fill the trench. The dummy gate structure is replaced with a gate structure.
    Type: Application
    Filed: April 27, 2015
    Publication date: February 4, 2016
    Inventors: PAN-KWI PARK, DONG-SUK SHIN, SEOK-JUN WON, WEON-HONG KIM, JAE-GON LEE