Abstract: A system for controlling the issuance of a "Sync In" signal by a disk file controller to a control unit to request a byte of data to arrive at the controller at the same predetermined time regardless of the propagation delay of the cables interconnecting the two units. The system includes a circuit arrangement for measuring the actual propagation delay of the interface cable by issuing a "Sync In" signal at a predetermined time and detecting when the return "Sync Out" signal is received. The measured time is converted to a "Sync In" lead time in terms of bits and bytes. This value is stored and subsequently controls circuitry for issuing the "Sync In" pulse at a bit time which provides the exact lead time necessary for the "Sync Out" signal to arrive at the predetermined bit and byte time so that the data byte will be encoded and recorded at the predefined location on the moving magnetic disk.

Abstract: A control system for a serial data channel for a disk file is disclosed in which a microcontroller is used as the control means. The microcontroller has an input port and an output port, while the serial data channel has a data register. The connections of the data register to the input and output port and the parallel by bit input and output busses on which write data and read data is sent provides a plurality of different data transfer loops through the data register which can be selected under the control of the microcontroller. The arrangement permits functions to be achieved by the microcontroller that heretofore were performed by another device connected to the controller or by special hardware.

Abstract: A system is disclosed for generating a plurality of error correcting check ECC bytes from a block of data presented to the system in serial by byte form. The system employs a plurality of ECC channels which operate in parallel with the channels generating check bytes from interleaved subsets of the data block. One channel generates an ECC parity check byte for each interleaved subset while another channel generates an ECC locator check byte for each interleaved subset of data. The ECC locator check byte for each subset represents the parity or modulo 2 sum of bit positions which are selected systematically in accordance with a predefined m sequence which is unique to each channel that generates locator check bytes. Error patterns greater than the number of bits in one byte are correctable, as are error patterns which are less than the number of bits in one byte but extend across byte boundaries of two adjacent bytes in different subsets.

Abstract: A system which employs a parallel to serial converter and a serial shift register encoder for encoding a multibyte sync pattern in a fixed rate variable word length run-length limited code wherein less than a single character of data is supplied to the encoder from the parallel to serial converter to encode the multibyte sync pattern. The system provides for feeding a first portion of the encoded sync pattern back to the encoder through a serial decoder which provides a serial bit stream that is identical to the initial pattern provided to the encoder. Suitable control circuitry is employed to control the phasing of the end of the initial bit stream and the beginning of the decoded bit stream fed back to the encoder. Once the feedback path is established, the total length of the encoded sync pattern is independent of the single character initially supplied to the encoder.