Patents by Inventor Wilbur G. Catabay

Wilbur G. Catabay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6391795
    Abstract: A composite layer of low k silicon oxide dielectric material is formed on an oxide layer of an integrated circuit structure on a semiconductor substrate having closely spaced apart metal lines thereon. The composite layer of low k silicon oxide dielectric material exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines, deposition rates in other regions comparable to standard k silicon oxide, and reduced via poisoning characteristics. The composite layer of low k silicon oxide dielectric material is formed by depositing, in high aspect ratio regions between closely spaced apart metal lines, a first layer of low k silicon oxide dielectric material exhibiting void-free deposition properties until the resulting deposition of low k silicon oxide dielectric material reaches the level of the top of the metal lines on the oxide layer.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: May 21, 2002
    Assignee: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Richard Schinella
  • Patent number: 6368979
    Abstract: A dual damascene type of structure of vias and trenches formed using layers of low k dielectric material is disclosed, and a process for making same without damage to the low k dielectric material during removal of photoresist masks used respectively in the formation of the pattern of via openings and the pattern of trench openings in the layers of low k dielectric material. Damage to the low k dielectric material is avoided by forming a first layer of low k dielectric material on an integrated circuit structure; forming a first hard mask layer over the first layer of low k dielectric material; forming over the first hard mask layer a first photoresist mask having a pattern of via openings therein; and then etching the first hard mask layer through the first photoresist mask to form a first hard mask having the pattern of vias openings replicated therein, using an etch system which will also remove the first photoresist mask.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: April 9, 2002
    Assignee: LSI Logic Corporation
    Inventors: Zhihai Wang, Wilbur G. Catabay, Joe W. Zhao
  • Patent number: 6350700
    Abstract: A low k carbon-doped silicon oxide dielectric material dual damascene structure is formed by improvements to a process wherein a first photoresist mask is used to form via openings through a first layer of low k carbon-doped silicon oxide dielectric material, followed by removal of the first photoresist mask; and wherein a second photoresist mask is subsequently used to form trenches in a second layer of low k carbon-doped silicon oxide dielectric material corresponding to a desired pattern of metal interconnects for an integrated circuit structure, followed by removal of the second photoresist mask.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: February 26, 2002
    Assignee: LSI Logic Corporation
    Inventors: Richard D. Schinella, Wilbur G. Catabay, Philippe Schoenborn
  • Patent number: 6346490
    Abstract: Damaged surfaces of a low k carbon-containing silicon oxide dielectric material are treated with one or more carbon-containing gases, and in the absence of an oxidizing agent, to inhibit subsequent formation of silicon-hydroxyl bonds when the damaged surfaces of the low k dielectric material are thereafter exposed to moisture. The carbon-containing gas treatment of the invention is carried out after the step of oxidizing or “ashing” the resist mask to remove the mask, but prior to exposure of the damaged surfaces of the low k dielectric material to moisture. Optionally, the carbon-containing gas treatment may also be carried out after the initial step of etching the low k carbon-containing silicon oxide dielectric material to form vias or contact openings as well, particularly when exposure of the damaged surfaces of the low k dielectric material to moisture after the via etching step and prior to the resist removing oxidation step is possible.
    Type: Grant
    Filed: April 5, 2000
    Date of Patent: February 12, 2002
    Assignee: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Wei-Jen Hsia, Alex Kabansky
  • Patent number: 6297555
    Abstract: A method of forming titanium nitride barrier layers that are highly conformal, have high step coverage and low resistivity through a two stage deposition process is described. Low temperature deposition of titanium nitride barrier layer provides material of high conformity and good step coverage but of high resistivity. High temperature deposition of titanium nitride barrier layer yields material of low resistivity. Thus, a titanium nitride barrier layer deposited in separate steps at low temperature and high temperature by the method of the present invention is particularly suited for use in modern devices of increasing density that are characterized by narrow and deep contact holes.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: October 2, 2001
    Assignee: LSI Logic Corporation
    Inventors: Joe W. Zhao, Wei-Jen Hsia, Wilbur G. Catabay
  • Patent number: 6232658
    Abstract: The invention comprises a process for forming a dielectric film having a compressive stress exhibited in the layers deposited onto an integrated circuit structure. This process includes depositing a first thin layer of dielectric material onto an integrated circuit structure, then exposing the integrated circuit structure to an elevated temperature. Then a second thin layer of dielectric material is deposited immediately overtop of the first thin layer of dielectric material, and then the integrated circuit structure is again exposed to an elevated temperature. The process is carried out to insure that the composite layer comprising the first and second deposited thin dielectric layers, after heat treatment, exhibits a residual stress which is compressive.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: May 15, 2001
    Assignee: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Wei-Jen Hsia, Joe W. Zhao
  • Patent number: 6204192
    Abstract: A process is provided for removing etch residues from one or more openings formed in one or more layers of a low dielectric constant insulation material over a copper metal interconnect layer of an integrated circuit structure which includes cleaning exposed portions of the surface of the copper interconnect layer at the bottom of the one or more openings, the process comprising providing an anisotropic hydrogen plasma to cause a chemical reaction between ions in the plasma and the etch residues in the bottom of the one or more opening, including copper oxide on the exposed copper surface, to thereby clean the exposed portions of the copper surface, and to remove the etch residues without sputtering the copper at the bottom of the opening.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: March 20, 2001
    Assignee: LSI Logic Corporation
    Inventors: Joe W. Zhao, Wei-Jen Hsia, Wilbur G. Catabay
  • Patent number: 6028015
    Abstract: A process is described for treating damaged surfaces of a low dielectric constant organo silicon oxide insulation layer of an integrated circuit structure to inhibit absorption of moisture which comprises treating such damaged surfaces of said organo silicon oxide insulation layer with a hydrogen plasma. The treatment with hydrogen plasma causes hydrogen to bond to silicon atoms with dangling bonds in the damaged surface of the organo silicon oxide layer to replace organic material severed from such silicon atoms at the damaged surface, whereby absorption of moisture in the damaged surface of the organo silicon oxide layer, by bonding of such silicon dangling bonds with moisture, is inhibited.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: February 22, 2000
    Assignee: LSI Logic Corporation
    Inventors: Zhihai Wang, Wilbur G. Catabay, Joe W. Zhao
  • Patent number: 5994775
    Abstract: The invention comprises an integrated circuit structure, and a process for making same, comprising a via/contact opening in a dielectric layer; a CVD layer of titanium nitride having a thickness of at least about 50 Angstroms, but not exceeding about 200 Angstroms, on the sidewall and bottom surfaces of the via/contact opening to provide adherence of the filler material to the underlying and sidewall surface of the opening; a CVD barrier layer of tungsten, having a thickness of about 50 Angstroms, but not exceeding about 300 Angstroms, formed over the titanium nitride layer; and the remainder of the via/contact opening filled with a highly conductive metal selected from the group consisting of copper, CVD aluminum, and force-filled aluminum.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: November 30, 1999
    Assignee: LSI Logic Corporation
    Inventors: Joe W. Zhao, Wilbur G. Catabay
  • Patent number: 5956613
    Abstract: A method of depositing a low carbon content, high density TiN thin film on a substrate. A substrate is placed within a deposition chamber, and the pressure within the deposition chamber is adjusted to the deposition pressure. A portion of the total thickness desired of the TiN thin film is deposited. The portion of the TiN thin film contains an amount of carbon. Carbon is scavenged from the portion of the TiN thin film deposited by introducing scavenger gases into the deposition chamber. The scavenger gases are chosen so as to be reactive with carbon. The pressure within the deposition chamber is adjusted to the scavenger pressure, and a plasma of the scavenger gases is created within the deposition chamber. The steps from deposition through scavenging are repeated until the desired thickness of TiN is deposited, and the substrate having the desired thickness of TiN deposited thereon is removed from the deposition chamber.
    Type: Grant
    Filed: December 27, 1995
    Date of Patent: September 21, 1999
    Assignee: LSI Logic Corporation
    Inventors: Joe W. Zhao, Wilbur G. Catabay
  • Patent number: 5953631
    Abstract: A method is presented for depositing a low stress, highly conformal metal thin film, such as tungsten, on a substrate. A substrate is provided, and is heated to a first temperature. A first portion of the metal thin film is deposited on the substrate by reacting a first set of process gases. The deposition of the first portion of the metal thin film is stopped after a first length of time, and the substrate is heated to a second temperature, which is greater than the first temperature. A second portion of the metal thin film is deposited on the substrate by reacting a second set of process gases. The second portion of the metal thin film comprises the same metal as the first portion of the metal thin film. The deposition of the second portion of the metal thin film is stopped after a second length of time. Semiconductor devices having a low stress, highly conformal thin film are also described.
    Type: Grant
    Filed: January 24, 1996
    Date of Patent: September 14, 1999
    Assignee: LSI Logic Corporation
    Inventors: Joe W. Zhao, Wilbur G. Catabay
  • Patent number: 5933757
    Abstract: An etch process selective to cobalt silicide is described for the selective removal of titanium and/or titanium nitride, unreacted cobalt, and cobalt reaction products other than cobalt silicide, remaining after the formation of cobalt silicide on an integrated circuit structure on a semiconductor substrate in preference to the removal of cobalt silicide. The first step comprises contacting the substrate with an aqueous mixture of ammonium hydroxide (NH.sub.4 OH) and hydrogen peroxide (H.sub.2 O.sub.2) to selectively remove any titanium and/or titanium nitride in preference to the removal of cobalt silicide. The second step comprises contacting the substrate with an aqueous mixture of phosphoric acid (H.sub.3 PO.sub.4), acetic acid (CH.sub.3 COOH), and nitric acid (HNO.sub.3) to selectively remove cobalt and cobalt reaction products (other than cobalt silicide) in preference to the removal of cobalt silicide.
    Type: Grant
    Filed: June 23, 1997
    Date of Patent: August 3, 1999
    Assignee: LSI Logic Corporation
    Inventors: Stephanie A. Yoshikawa, Wilbur G. Catabay
  • Patent number: 5902129
    Abstract: The formation of a cobalt silicide layer of uniform thickness over the source/drain regions and the polysilicon gate electrode of an MOS structure, which does not thin out adjacent the edges of the top surface of the polysilicon gate electrode, i.e., adjacent the oxide spacers, is achieved by first forming a titanium capping layer over a cobalt layer deposited over the MOS structure prior to formation of the cobalt silicide, and while excluding oxygen-bearing gases from the cobalt surface prior to the deposition of the titanium capping layer.
    Type: Grant
    Filed: April 7, 1997
    Date of Patent: May 11, 1999
    Assignee: LSI Logic Corporation
    Inventors: Stephanie A. Yoshikawa, Zhihai Wang, Wilbur G. Catabay
  • Patent number: 5895267
    Abstract: A method of forming titanium nitride barrier layers that are highly conformal, have high step coverage and low resistivity through a two stage deposition process is described. Low temperature deposition of titanium nitride barrier layer provides material of high conformity and good step coverage but of high resistivity. High temperature deposition of titanium nitride barrier layer yields material of low resistivity. Thus, a titanium nitride barrier layer deposited in separate steps at low temperature and high temperature by the method of the present invention is particularly suited for use in modern devices of increasing density that are characterized by narrow and deep contact holes.
    Type: Grant
    Filed: July 9, 1997
    Date of Patent: April 20, 1999
    Assignee: LSI Logic Corporation
    Inventors: Joe W. Zhao, Wei-Jen Hsia, Wilbur G. Catabay
  • Patent number: 5789028
    Abstract: A process and apparatus are described for inhibiting, but not completely eliminating, the deposition of titanium nitride by MOCVD on the end edge of a semiconductor substrate which comprises directing toward such substrate end edge a flow of one or more deposition-inhibiting gases in a direction which substantially opposes the flow of process gases toward the end edges of the substrate. This flow of deposition-inhibiting gases toward the end edges of the substrate reduces the deposition of the titanium nitride at the end edge of the semiconductor substrate either by directing some of the flow of process gases away from such end edge of the substrate, or by locally diluting such process gases in the region of the deposition chamber adjacent the end edge of the substrate, or by some combination of the foregoing.
    Type: Grant
    Filed: March 4, 1997
    Date of Patent: August 4, 1998
    Assignee: LSI Logic Corporation
    Inventors: Joe W. Zhao, Wei-Jen Hsia, Wilbur G. Catabay
  • Patent number: 5770520
    Abstract: Described is a barrier layer in an integrated circuit structure which is formed in a via or contact opening over an underlying material in which diffusion of the underlying material (or filler material deposited over the barrier layer) through the barrier layer is inhibited without unduly increasing the thickness and resistivity of the barrier layer. This is accomplished by substituting an amorphous material for the crystalline titanium nitride to thereby eliminate the present of grain boundaries which are believed to provide the diffusion path through the titanium nitride material. In a preferred embodiment, the amorphous barrier layer comprises an amorphous ternary Ti--Si--N material formed using a source of titanium, a source of silicon, and a source of nitrogen. None of the source materials should contain oxygen to avoid formation of undesirable oxides which would increase the resistivity of the barrier layer.
    Type: Grant
    Filed: December 5, 1996
    Date of Patent: June 23, 1998
    Assignee: LSI Logic Corporation
    Inventors: Joe W. Zhao, Zhihai Wang, Wilbur G. Catabay
  • Patent number: 5660682
    Abstract: A method of removing material from an integrated circuit. The integrated circuit is placed within a reaction chamber, and a flow of argon and a flow of hydrogen are introduced into the reaction chamber, where the flow of hydrogen is greater than the flow of argon. The flows of argon and hydrogen are energized to form a plasma, and the material is removed from the integrated circuit by reaction of the material with the energized flows of argon and hydrogen to form gaseous products, which are pumped out of the reaction chamber. The plasma and flows of argon and hydrogen are discontinued when a desired amount of material has been removed, and the integrated circuit is removed from the reaction chamber.
    Type: Grant
    Filed: March 14, 1996
    Date of Patent: August 26, 1997
    Assignee: LSI Logic Corporation
    Inventors: Joe W. Zhao, Zhihai Wang, Wilbur G. Catabay
  • Patent number: 5635244
    Abstract: Disclosed is a wafer clamp which holds a wafer in place during chemical vapor deposition processes. The wafer clamp includes (1) a clamp body having an inner facing portion and an outer facing portion; and (2) an overhang member attached to and extending inwardly from the inner facing portion of the clamp body. The clamp is designed such that when it holds the wafer, the overhang member extends over the wafer's peripheral region and is separated from that peripheral region by at least a predefined distance. The peripheral region is a region on the wafer's upper face that resides near the perimeter of the upper face. The predefined distance is chosen such that during deposition, a layer of material does not contact both the wafer face and the overhang member. The predefined distance is at least about 100 times the thickness of the layer of material.
    Type: Grant
    Filed: August 28, 1995
    Date of Patent: June 3, 1997
    Assignee: LSI Logic Corporation
    Inventors: Mark I. Mayeda, Wilbur G. Catabay, Joe W. Zhao