Abstract: A power combiner for an outphasing amplifier system comprises an output terminal, a first input terminal, a first inductor, and a first capacitor, wherein the first input terminal is connected to ground via the first inductor and the first input terminal is connected to the output terminal via the first capacitor. The power combiner further comprises a second input terminal, a second capacitor, and a second inductor, wherein the second input terminal is connected to ground via the second capacitor and the second input terminal is connected to the output terminal via the second inductor. The first capacitor can have a same capacitance as the second capacitor and the first inductor has a same inductance as the second inductor.

Abstract: A method for depositing a layer on a semiconductor wafer by vapor deposition in a process chamber, involves removing native oxide from a surface of the wafer; and then depositing an epitaxial layer with a thickness of at least 40 ?m on the surface of the wafer by introducing a silicon containing gas and a carrier gas into the process chamber, wherein the flow rate of the silicon containing gas is lower than 10 standard liters per minute and the flow rate of the carrier gas is at least 40 standard liters per minute.

Abstract: A method for depositing a layer on a semiconductor wafer by vapor deposition in a process chamber, involves removing native oxide from a surface of the wafer; and then depositing an epitaxial layer with a thickness of at least 40 ?m on the surface of the wafer by introducing a silicon containing gas and a carrier gas into the process chamber, wherein the flow rate of the silicon containing gas is lower than 10 standard liters per minute and the flow rate of the carrier gas is at least 40 standard liters per minute.

Abstract: An integrated circuit, comprising a single-ended pin for transmitting and/or receiving an RF signal. A first matching network is configured to match an impedance of the RF signal. A second matching network is configured to match an impedance of an on-chip differential circuit. A third matching network is configured to match an impedance of an on-chip single-ended circuit, wherein the third matching network is connectable to the first matching network. A transformer is connected or connectable to the second matching network and to the first matching network. Switches control an operating mode of the integrated circuit The second matching network is connected with the first matching network via the transformer, or the third matching network is connected with the first matching network.

Abstract: An integrated circuit, comprising a single-ended pin for transmitting and/or receiving an RF signal. A first matching network is configured to match an impedance of the RF signal. A second matching network is configured to match an impedance of an on-chip differential circuit. A third matching network is configured to match an impedance of an on-chip single-ended circuit, wherein the third matching network is connectable to the first matching network. A transformer is connected or connectable to the second matching network and to the first matching network. Switches control an operating mode of the integrated circuit The second matching network is connected with the first matching network via the transformer, or the third matching network is connected with the first matching network.