Patents by Inventor Willem Zwart
Willem Zwart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230052112Abstract: A force sensing system for determining if a user input has occurred, the system comprising: an input channel, to receive an input from at least one force sensor; an activity detection stage, to monitor an activity level of the input from the at least one force sensor and, responsive to an activity level which may be indicative of a user input being reached, to generate an indication that an activity has occurred at the force sensor; and an event detection stage to receive said indication, and to determine if a user input has occurred based on the received input from the at least one force sensor.Type: ApplicationFiled: October 7, 2022Publication date: February 16, 2023Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Hamid SEPEHR, Pablo PESO PARADA, Willem ZWART, Tom BIRCHALL, Michael Allen KOST, Tejasvi DAS, Siddharth MARU, Matthew BEARDSWORTH, Bruce E. DUEWER
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Patent number: 11507267Abstract: A force sensing system for determining if a user input has occurred, the system comprising: an input channel, to receive an input from at least one force sensor; an activity detection stage, to monitor an activity level of the input from the at least one force sensor and, responsive to an activity level which may be indicative of a user input being reached, to generate an indication that an activity has occurred at the force sensor; and an event detection stage to receive said indication, and to determine if a user input has occurred based on the received input from the at least one force sensor.Type: GrantFiled: September 10, 2021Date of Patent: November 22, 2022Assignee: Cirrus Logic, Inc.Inventors: Hamid Sepehr, Pablo Peso Parada, Willem Zwart, Tom Birchall, Michael Allen Kost, Tejasvi Das, Siddharth Maru, Matthew Beardsworth, Bruce E. Duewer
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Patent number: 11269509Abstract: A force sensing system for determining if a user input has occurred, the system comprising: an input channel, to receive an input from at least one force sensor; an activity detection stage, to monitor an activity level of the input from the at least one force sensor and, responsive to an activity level which may be indicative of a user input being reached, to generate an indication that an activity has occurred at the force sensor; and an event detection stage to receive said indication, and to determine if a user input has occurred based on the received input from the at least one force sensor.Type: GrantFiled: October 21, 2020Date of Patent: March 8, 2022Assignee: Cirrus Logic, Inc.Inventors: Hamid Sepehr, Pablo Peso Parada, Willem Zwart, Tom Birchall, Michael Allen Kost, Tejasvi Das, Siddharth Maru, Matthew Beardsworth, Bruce E. Duewer
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Publication number: 20210405840Abstract: A force sensing system for determining if a user input has occurred, the system comprising: an input channel, to receive an input from at least one force sensor; an activity detection stage, to monitor an activity level of the input from the at least one force sensor and, responsive to an activity level which may be indicative of a user input being reached, to generate an indication that an activity has occurred at the force sensor; and an event detection stage to receive said indication, and to determine if a user input has occurred based on the received input from the at least one force sensor.Type: ApplicationFiled: September 10, 2021Publication date: December 30, 2021Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Hamid SEPEHR, Pablo PESO PARADA, Willem ZWART, Tom BIRCHALL, Michael Allen KOST, Tejasvi DAS, Siddharth MARU, Matthew BEARDSWORTH, Bruce E. DUEWER
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Publication number: 20210034213Abstract: A force sensing system for determining if a user input has occurred, the system comprising: an input channel, to receive an input from at least one force sensor; an activity detection stage, to monitor an activity level of the input from the at least one force sensor and, responsive to an activity level which may be indicative of a user input being reached, to generate an indication that an activity has occurred at the force sensor; and an event detection stage to receive said indication, and to determine if a user input has occurred based on the received input from the at least one force sensor.Type: ApplicationFiled: October 21, 2020Publication date: February 4, 2021Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Hamid SEPEHR, Pablo PESO PARADA, Willem ZWART, Tom BIRCHALL, Michael Allen KOST, Tejasvi DAS, Siddharth MARU, Matthew BEARDSWORTH, Bruce E. DUEWER
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Patent number: 10860202Abstract: A force sensing system for determining if a user input has occurred, the system comprising: an input channel, to receive an input from at least one force sensor; an activity detection stage, to monitor an activity level of the input from the at least one force sensor and, responsive to an activity level which may be indicative of a user input being reached, to generate an indication that an activity has occurred at the force sensor; and an event detection stage to receive said indication, and to determine if a user input has occurred based on the received input from the at least one force sensor.Type: GrantFiled: May 24, 2019Date of Patent: December 8, 2020Assignee: Cirrus Logic, Inc.Inventors: Hamid Sepehr, Pablo Peso Parada, Willem Zwart, Tom Birchall, Michael Allen Kost, Tejasvi Das, Siddharth Maru, Matthew Beardsworth, Bruce E. Duewer
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Patent number: 10642570Abstract: A method of compensating for a round-trip transmission delay in an audio system comprising: a portable communications device; an audio accessory; and a cable, suitable for connecting the portable communications device and the audio accessory, having at least one wire and being detachable from at least one of the portable communications device and the audio accessory. At first times, a first synchronisation data pattern is transmitted on the at least one wire from said device to said accessory, wherein said first synchronisation data pattern comprises first signal level transitions on the at least one wire, synchronised to a master transmission clock. At second times, a second synchronisation data pattern is transmitted on the at least one wire from said accessory to said device, wherein said second synchronisation data pattern comprises second signal level transitions at timings that are set based on a delay value stored in said accessory.Type: GrantFiled: October 31, 2017Date of Patent: May 5, 2020Assignee: Cirrus Logic, Inc.Inventor: Willem Zwart
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Publication number: 20200133455Abstract: A force sensing system for determining if a user input has occurred, the system comprising: an input channel, to receive an input from at least one force sensor; an activity detection stage, to monitor an activity level of the input from the at least one force sensor and, responsive to an activity level which may be indicative of a user input being reached, to generate an indication that an activity has occurred at the force sensor; and an event detection stage to receive said indication, and to determine if a user input has occurred based on the received input from the at least one force sensor.Type: ApplicationFiled: May 24, 2019Publication date: April 30, 2020Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Hamid SEPEHR, Pablo PESO PARADA, Willem ZWART, Tom BIRCHALL, Michael Allen KOST, Tejasvi DAS, Siddharth MARU, Matthew BEARDSWORTH, Bruce E. DUEWER
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Patent number: 10567214Abstract: Communication circuitry, comprising: N communication nodes being clock-candidate nodes, where N?2; N communication units for communication using respective communication protocols, and connected or connectable to receive respective clock signals for communication under their respective communication protocols via respective said clock-candidate nodes; and a control unit configured, in a decision operation, to monitor the clock-candidate nodes and decide which of the communication protocols is in use dependent on at which of the clock-candidate nodes a received clock signal is detected, wherein at least one said communication unit is connected or connectable to receive and/or transmit data under its respective communication protocol via at least one said clock-candidate node other than the clock-candidate node via which that communication unit is to receive its respective clock signal.Type: GrantFiled: April 30, 2018Date of Patent: February 18, 2020Assignee: Cirrus Logic, Inc.Inventors: Alastair Mark Boomer, Erich Paul Zwyssig, Gavin Alexander Waite, Willem Zwart
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Publication number: 20190334756Abstract: Communication circuitry, comprising: N communication nodes being clock-candidate nodes, where N?2; N communication units for communication using respective communication protocols, and connected or connectable to receive respective clock signals for communication under their respective communication protocols via respective said clock-candidate nodes; and a control unit configured, in a decision operation, to monitor the clock-candidate nodes and decide which of the communication protocols is in use dependent on at which of the clock-candidate nodes a received clock signal is detected, wherein at least one said communication unit is connected or connectable to receive and/or transmit data under its respective communication protocol via at least one said clock-candidate node other than the clock-candidate node via which that communication unit is to receive its respective clock signal.Type: ApplicationFiled: April 30, 2018Publication date: October 31, 2019Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Alastair Mark BOOMER, Erich Paul ZWYSSIG, Gavin Alexander WAITE, Willem ZWART
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Publication number: 20190267009Abstract: According to embodiments described herein there is provided methods and apparatus for authenticating a first audio signal received at a device. The method comprises receiving the first audio signal at a first input, wherein the first input is for receiving audio signals from a first microphone, receiving a second audio signal at a second input from a second microphone; and comparing a third audio signal derived from the first audio signal to a fourth audio signal derived from the second audio signal. The method further comprises determining, based on the comparison, whether the first audio signal and the second audio signal meet a predetermined condition, wherein the predetermined condition indicates that the first audio signal and the second audio signal are both derived from a common acoustic signal; and using the first audio signal as an input to a voice biometrics module responsive to a determination that the first audio signal and the second audio signal meet the condition.Type: ApplicationFiled: February 27, 2018Publication date: August 29, 2019Applicant: Cirrus Logic International Semiconductor Ltd.Inventor: Willem ZWART
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Patent number: 10305670Abstract: A method for transferring data over a half-duplex wired communications link, comprises, in each of a plurality of frames: transferring a synchronization data pattern in a first direction; transferring first payload data in the first direction; transferring second payload data in a second direction opposite to the first direction; and transferring control data, wherein the format of the frame is such that, irrespective of whether the control data is transferred in the first direction or in the second direction, there is only one pair of reversals of a direction of data transfer in each frame.Type: GrantFiled: June 28, 2018Date of Patent: May 28, 2019Assignee: Cirrus Logic, Inc.Inventor: Willem Zwart
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Patent number: 10305671Abstract: Synchronous, differential signaling may be performed over a communications path through a wired connection between a master device and a slave device to provide high-bandwidth and/or low-latency communications. Flexibility may be provided in the signaling protocol by providing for a configurable frame structure. Flexibility may be provided in mapping of data streams to bit slots in a frame, varying a number of downlink and uplink slots, configuring a number of turnarounds and locations of the turnarounds within a frame, configuring location and number of control word bit (CWB) slots in a frame, and/or adjusting a clock frequency of the communications link.Type: GrantFiled: May 19, 2016Date of Patent: May 28, 2019Assignee: Cirrus Logic, Inc.Inventors: Bhoodev Kumar, Muraleedharan Ramakrishnan, Vivek Oppula, Thomas Hoff, Willem Zwart
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Patent number: 10298379Abstract: A method for transferring data over a half-duplex wired communications link, comprises, in each of a plurality of frames: transferring a synchronization data pattern in a first direction; transferring first payload data in the first direction; transferring second payload data in a second direction opposite to the first direction; and transferring control data, wherein the format of the frame is such that, irrespective of whether the control data is transferred in the first direction or in the second direction, there is only one pair of reversals of a direction of data transfer in each frame.Type: GrantFiled: December 13, 2017Date of Patent: May 21, 2019Assignee: Cirrus Logic, Inc.Inventor: Willem Zwart
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Patent number: 10218535Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.Type: GrantFiled: February 19, 2018Date of Patent: February 26, 2019Assignee: Cirrus Logic, Inc.Inventors: Willem Zwart, John Bruce Bowlerwell, Michael Page, Alastair Boomer
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Publication number: 20180309564Abstract: A method for transferring data over a half-duplex wired communications link, comprises, in each of a plurality of frames: transferring a synchronization data pattern in a first direction; transferring first payload data in the first direction; transferring second payload data in a second direction opposite to the first direction; and transferring control data, wherein the format of the frame is such that, irrespective of whether the control data is transferred in the first direction or in the second direction, there is only one pair of reversals of a direction of data transfer in each frame.Type: ApplicationFiled: June 28, 2018Publication date: October 25, 2018Applicant: Cirrus Logic International Semiconductor Ltd.Inventor: Willem ZWART
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Publication number: 20180307555Abstract: A data transmitter is configured for transmitting multiple payload data streams in a frame format, wherein each frame comprises multiple rows, and each row comprises multiple bit slots. The data transmitter comprises: configuration storage circuitry, for storing frame format configuration data; an input, for receiving the multiple payload data streams; data multiplexing circuitry, for Combining the multiple payload data streams in accordance with the stored frame format configuration data to form a combined payload data stream; and redundancy code generator circuitry, for receiving the combined payload data stream, and generating check bit data therefrom. The data multiplexing circuitry is further configured for multiplexing the combined payload data stream and the check bit data into data for transmission in said frame format.Type: ApplicationFiled: June 24, 2016Publication date: October 25, 2018Applicant: Cirus Logic International Semiconductor Limited.Inventor: Willem ZWART
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Patent number: 10042796Abstract: An audio system comprises a master device; a slave device; and a wired connection, suitable for connecting the master device and the slave device, and having at least two wires.Type: GrantFiled: October 30, 2015Date of Patent: August 7, 2018Assignee: Cirrus Logic, Inc.Inventor: Willem Zwart
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Patent number: 10027514Abstract: A system comprises a first module and a second module, connected by a transmission line comprising first and second wires. The first module includes common mode voltage circuitry, for imposing a common mode voltage onto the first and second wires. The first module includes signal generation circuitry, for generating a signal voltage in response to first data, and for imposing the signal voltage as a differential signal onto the first and second wires during periods when the first module has first data to transmit. The second module includes current generation circuitry, for generating a signal current in response to second data, and for injecting the signal current as a differential current onto the first and second wires during periods when the second module has second data to transmit. The first module includes respective resistances connected to the first and second wires.Type: GrantFiled: October 30, 2015Date of Patent: July 17, 2018Assignee: Cirrus Logic, Inc.Inventors: Willem Zwart, Bhupendra Singh Manola
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Publication number: 20180176034Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.Type: ApplicationFiled: February 19, 2018Publication date: June 21, 2018Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Willem ZWART, John Bruce BOWLERWELL, Michael PAGE, Alastair BOOMER