Abstract: In one embodiment of the invention, a programmable logic device, such as an FPGA, has programmable I/O circuits that can be programmed into any one of a number of different operating modes before configuration is completed. As such, the same set of I/O circuits and corresponding I/O pads can be used to configure the device using different configuration interfaces having different interface signaling requirements. Such a device may be able to be implemented using fewer I/O pads than conventional devices that employ a different set of I/O pads for each different type of configuration interface supported by the device.

Abstract: In one embodiment of the invention, a receiver has two mux circuits, two receiver circuits, and a mixer. The muxes select first and second input signals for the receiver circuits. A p-type transistor in a transmission gate in each mux is connected (i) at its channel nodes between a pad and the mux output and (ii) to receive a control signal at its gate node. Control circuitry for the p-type transistor implements a threshold reduction filter that ensures that a maximum voltage level at the mux output is at least a threshold below the mux's power supply voltage. Based on first and second input signals, the first receiver circuit generates first and second intermediate signals, and the second receiver circuit generates third and fourth intermediate signals. The mixer circuit combines the intermediate signals to generate first and second output signals, wherein the first and second receiver circuits effectively operate over different ranges of common-mode voltages.

Abstract: In one embodiment, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. A sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs. The temperature-independence and constant IV characteristic of the sense element and termination legs enable a single calibration circuit to simultaneously control multiple termination schemes operating at different termination voltage levels.

Abstract: In one embodiment of the invention, a bias signal monitor has two signal comparators that compare two (power supply) voltages at two different bias points and a logic circuit that processes the outputs from the two signal monitors to generate a bias signal monitor output signal. The logic circuit implements hysteresis-based processing such that (1) if both signal comparators are active (indicating that a first voltage is greater than the second voltage relative to both bias points), then the monitor output is active, (2) if both signal comparators are inactive (indicating that the first voltage is not greater than the second voltage relative to either bias point), then the monitor output is inactive, and (3) if one signal comparator is active and the other is inactive, then the monitor output keeps its previous value. This hysteresis characteristic prevents relatively small oscillations between the voltages from changing the monitor output.

Abstract: In one embodiment of the invention, a programmable level shifter can be selectively configured to operate in either a high-speed mode or a low-power mode. In both modes, the level shifter converts an input signal in one power supply domain into an output signal in another power supply domain. In the high-speed mode, p-type devices are configured as a current-mirror amplifier that provides the level shifter with relatively fast switching speed. In the low-power mode, the same p-type devices are configured as a cross-coupled latch that provides the level shifter with relatively low power consumption. Selectively enabled n-type devices provide the low-power mode with larger effective n-type devices to flip the cross-coupled latch formed by the p-type devices in the low-power mode.

Abstract: In one embodiment, an integrated circuit has configurable application circuitry that operates at any one of multiple available power supply voltages. PT-control circuitry, operating at a PT reference voltage, generates a PT-control signal indicative of variations in process and temperature. Application-control circuitry controls the configuration of the application circuitry based on the selected power supply voltage for the application circuitry and the PT-control signal, where the selected power supply voltage is independent of the PT reference voltage.

Abstract: In one embodiment of the invention, an integrated device has interface circuitry that includes a dynamic monitor that monitors the relative potential between (at least) two different power supplies to enable the device to react to over-voltage conditions such that appropriate selections can be made for which power supplies are selected for different components in the interface circuitry, such as output drivers and input receivers. The dynamic monitor enables over-voltage protection to be automatically implemented before the device has been configured, such as during the device's power-on state.

Abstract: A buffer for a programmable logic device has programmable current sink and source circuitry and an independently programmable common-mode voltage reference source. An amplifier, responsive to a common-mode voltage detector and the voltage reference source, forces a common-mode voltage of an output signal from the buffer to approximate the voltage from the common-mode voltage reference source.

Abstract: In one embodiment of the invention, a receiver has two mux circuits, two receiver circuits, and a mixer. The muxes select first and second input signals for the receiver circuits. A p-type transistor in a transmission gate in each mux is connected (i) at its channel nodes between a pad and the mux output and (ii) to receive a control signal at its gate node. Control circuitry for the p-type transistor implements a threshold reduction filter that ensures that a maximum voltage level at the mux output is at least a threshold below the mux's power supply voltage. Based on first and second input signals, the first receiver circuit generates first and second intermediate signals, and the second receiver circuit generates third and fourth intermediate signals. The mixer circuit combines the intermediate signals to generate first and second output signals, wherein the first and second receiver circuits effectively operate over different ranges of common-mode voltages.

Abstract: In one embodiment of the invention, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. The sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs.

Abstract: An improved output buffer having a digital output slew control and compensation for manufacturing process variations. Output slewing is accomplished by sequencing digital drive signals to paralleled output transistors. In one embodiment, a pre-driver sequences the drive signals by using the propagation delays of serially coupled digital logic gates to reduce power supply droop and/or ground bounce. The output transistors are turned off substantially simultaneously to avoid undesirable power supply DC current flow when the output buffer changes state. Programmably configuring the number of paralleled transistors that may be turned on at any given time allows a user to compensate for manufacturing process variations and determine the output impedance/drive capacity of the buffer.

Abstract: An apparatus includes an injection molding machine, a hot runner apparatus attached to the molding machine, and a mold defining a part cavity. The mold is attached to the molding machine and operably engages the hot runner apparatus. The hot runner apparatus has secondary nozzles that engage respective sprue assemblies on the mold for communicating melted plastic material to the mold cavity. Each sprue assembly includes a movably mounted sprue and a stress-reducing mechanism with spring washers that support the sprue to provide sufficient force to eliminate leaking at abutting contact surfaces against the secondary nozzles, but that allow limited movement of the sprue to reduce excessive stress focused on the respective sprues. Since the stress-reducing mechanism is located in the mold, each stress-reducing mechanism can be tailored to the particular needs of that particular mold and the particular melted material being processed.

Abstract: In one embodiment of the invention, a programmable termination structure has first and second termination circuits for corresponding pads and a programmable connection therebetween. The first termination circuit supports first and second sets of termination schemes. A shared resistor is part of at least one termination scheme in each set. The first termination circuit supports a termination scheme between the first pad and a user-defined node connected to an on-chip capacitor such that first pad is connected via the termination scheme to the on-chip capacitor. Control circuitry automatically turns on and off a termination scheme for bidirectional signaling supported by the first termination circuit, wherein (1) the control circuitry turns off the termination scheme if an output buffer is configured to present outgoing signals at the first pad and (2) the control circuitry turns on the termination scheme if the output buffer is disabled in order to terminate incoming signals received at the first pad.

Abstract: An integrated circuit having a transistor device and over-voltage protection circuitry. The transistor device is implemented in a technology having a specified operating-voltage range, the transistor device having gate, drain, source, and tub nodes, and the specified operating-voltage range having a specified maximum voltage. The over-voltage protection circuitry is adapted to apply gate and tub voltages to the gate and tub nodes, respectively. If at least one channel voltage applied to at least one of the drain and source nodes exceeds the specified maximum voltage, then the over-voltage protection circuitry controls at least one of the gate voltage and the tub voltage to inhibit one or more adverse effects to the transistor device.

Abstract: A buffer for a programmable device has source current circuitry, sink current circuitry, one or more input nodes, one or more output nodes, and switch circuitry. The source current circuitry can be programmably controlled to generate a plurality of different total source currents, and the sink current circuitry can be programmably controlled to generate a plurality of different total sink currents. The one or more input nodes can receive one or more input signals, and the one or more output nodes can present one or more output signals. The switch circuitry can selectively apply at least one of a total source current and a total sink current to the one or more output nodes based on the one or more input signals.

Abstract: An electrical system has a master circuit and an interface (I/F) circuit. The master circuit generates a master output signal. The I/F circuit receives an I/F input signal and a flag signal and generates an I/F output signal for application to a slave circuit, wherein the I/F input signal is based on the master output signal, and the interface circuit generates the L/F output signal either dependent on or independent of the I/F input signal as indicated by the flag signal.

Abstract: Systems and methods are disclosed to provide static and/or dynamic phase adjustments to a data signal relative to a clock signal. For example, the data signal may be delayed by a coarse delay and/or a fine delay to match the timing of the clock signal independently for each input path (e.g., per input pad). The delay may be as a function of positive and/or negative clock edges.

Abstract: Systems and methods are disclosed herein to implement signal delay in integrated circuits. For example, in accordance with an embodiment of the present invention, a master delay circuit may digitally control one or more slave delay cells to support various applications of a programmable logic device.

Abstract: A programmable logic device (PLD), such as a field programmable gate array (FPGA) has a logic core surrounded on one or more sides by an input/output (I/O) interface having one or more programmable I/O buffers (PIBs). At least one PIB can be programmed to perform two or more of (a) a pass-through data input mode, (b) an input register mode; (c) a double data rate (DDR) input mode, (d) one or more demux input modes, (e) one or more DDR demux input modes. In addition or alternatively, at least one PIB can be programmed to perform two or more of (a) a pass-through data output mode, (b) an output register mode, (c) a DDR output mode, (d) one or more mux output modes, and (e) one or more DDR mux output modes. As such, devices of the present invention are flexible enough to support both low-rate and high-rate interface applications, while efficiently using device resources.

Abstract: A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.