Patents by Inventor William French

William French has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Forming a ferromagnetic alloy core for high frequency micro fabricated inductors and transformers
    Patent number: 8450830
    Abstract: A plurality of sequential electro-deposition, planarization and insulator deposition steps are performed over a patterned thick photoresist film to form a laminated ferromagnetic alloy core for micro-fabricated inductors and transformers. The use of a plurality of contiguous thin laminations within deep patterns on non-removable photoresist film provides sufficient volume of magnetic film in, for example, high frequency applications, and reduces eddy current loss at high frequency.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: May 28, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, William French, Andrei Papou, Dok Won Lee
  • SYSTEM AND METHOD OF GALVANIC ISOLATION IN DIGITAL SIGNAL TRANSFER INTEGRATED CIRCUITS UTILIZING CONDUCTIVITY MODULATION OF SEMICONDUCTOR SUBSTRATE
    Publication number: 20130062725
    Abstract: A galvanic isolation system provides galvanic isolation in digital transfer integrated circuits by using conductivity modulation of the semiconductor substrate. Modulation of the conductivity of the substrate affects eddy current losses of a (differential) RF inductor that is isolated from the substrate by a sufficient amount of dielectric material, which provides a basis for signal transfer from the modulated substrate to the inductor across the isolation barrier.
    Type: Application
    Filed: September 12, 2011
    Publication date: March 14, 2013
    Inventors: Peter J. Hopper, Peter Smeys, William French, Andrei Papou, Chaudhuri Dutt Adilti
  • FORMING A FERROMAGNETIC ALLOY CORE FOR HIGH FREQUENCY MICRO FABRICATED INDUCTORS AND TRANSFORMERS
    Publication number: 20130062729
    Abstract: A plurality of sequential electro-deposition, planarization and insulator deposition steps are performed over a patterned thick photoresist film to form a laminated ferromagnetic alloy core for micro-fabricated inductors and transformers. The use of a plurality of contiguous thin laminations within deep patterns on non-removable photoresist film provides sufficient volume of magnetic film in, for example, high frequency applications, and reduces eddy current loss at high frequency.
    Type: Application
    Filed: September 12, 2011
    Publication date: March 14, 2013
    Inventors: Peter J. Hopper, William French, Andrei Papou, Dok Won Lee
  • Inductively coupled photodetector and method of forming an inductively coupled photodetector
    Patent number: 8390025
    Abstract: A photodetector detects the absence or presence of light by detecting a change in the inductance of a coil. The magnetic field generated when a current flows through the coil passes through an electron-hole generation region. Charged particles in the electron-hole generation region come under the influence of the magnetic field, and generate eddy currents whose magnitudes depend on whether light is absent or present. The eddy currents generate a magnetic field that opposes the magnetic field generated by current flowing through the coil.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: March 5, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Ann Gabrys, Peter J. Hopper, William French, Kyuwoon Hwang
  • System and method of galvanic isolation in digital signal transfer integrated circuits utilizing conductivity modulation of semiconductor substrate
    Patent number: 8390093
    Abstract: A galvanic isolation system provides galvanic isolation in digital transfer integrated circuits by using conductivity modulation of the semiconductor substrate. Modulation of the conductivity of the substrate affects eddy current losses of a (differential) RF inductor that is isolated from the substrate by a sufficient amount of dielectric material, which provides a basis for signal transfer from the modulated substrate to the inductor across the isolation barrier.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: March 5, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Smeys, William French, Andrei Papou, Aditi Dutt Chaudhuri
  • SEMICONDUCTOR STRUCTURE WITH GALVANICALLY-ISOLATED SIGNAL AND POWER PATHS
    Publication number: 20130049916
    Abstract: A galvanic die has signal structures and a transformer structure that provide galvanically-isolated signal and power paths for a high-voltage die and a low-voltage die, which are both physically supported by the galvanic die and electrically connected to the signal and transformer structures of the galvanic die.
    Type: Application
    Filed: August 26, 2011
    Publication date: February 28, 2013
    Inventors: Ann Gabrys, William French, Peter J. Hopper, Dok Won Lee, Peter Johnson
  • Semiconductor structure with galvanically-isolated signal and power paths
    Patent number: 8378776
    Abstract: A galvanic die has signal structures and a transformer structure that provide galvanically-isolated signal and power paths for a high-voltage die and a low-voltage die, which are both physically supported by the galvanic die and electrically connected to the signal and transformer structures of the galvanic die.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: February 19, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Ann Gabrys, William French, Peter J. Hopper, Dok Won Lee, Peter Johnson
  • Method of batch trimming circuit elements
    Patent number: 8378460
    Abstract: Multiple wafers that each has multiple high-precision circuits and corresponding trim control circuits are batch trimmed in a process where each wafer is formed to include openings that expose trimmable circuit elements that are internal to the circuitry of the high-precision circuits. The high-precision circuits and trim control circuits are electrically activated during the trimming phase by metal traces that run along the saw streets. The method attaches a wafer contact structure to each wafer to electrically activate the metal traces. The method places the wafers with the wafer contact structures into a solution where the exposed trimmable circuit elements are electroplated or anodized when the actual output voltage of a high-precision circuit does not match the predicted output voltage of the high-precision circuit.
    Type: Grant
    Filed: December 24, 2010
    Date of Patent: February 19, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Peter Smeys, William French
  • Method of forming high capacitance semiconductor capacitors with a single lithography step
    Patent number: 8377792
    Abstract: An interdigitated semiconductor capacitor with a large number of plates and a capacitance in the micro-farad range is formed on a wafer with only a single lithography step by depositing each odd layer of metal through a first shadow mask that lies spaced apart from the wafer, and each even layer of metal through a second shadow mask that lies spaced apart from the wafer.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: February 19, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, William French, Peter Smeys, Peter Johnson
  • Galvanic Isolation Fuse and Method of Forming the Fuse
    Publication number: 20130037908
    Abstract: The spikes in current and voltage that result from the failure of a galvanic dielectric layer are safely contained by a galvanic isolation fuse that pops and forms and open circuit between a high-voltage die and a low-voltage die in response to the failure of the galvanic dielectric layer.
    Type: Application
    Filed: August 12, 2011
    Publication date: February 14, 2013
    Inventors: Peter J. Hopper, William French, Ann Gabrys, Martin Fallon
  • Semiconductor Structure with Galvanic Isolation
    Publication number: 20130037909
    Abstract: Galvanic isolation between a high-voltage die and a low-voltage die in a multi-die chip is provided by a galvanic isolation die that physically supports the high-voltage die and the low-voltage die, and provides capacitive structures with high breakdown voltages that allow the high-voltage die to capacitively communicate with the low-voltage die.
    Type: Application
    Filed: August 9, 2011
    Publication date: February 14, 2013
    Inventors: William French, Peter J. Hopper, Ann Gabrys
  • Die-Sized Atomic Magnetometer and Method of Forming the Magnetometer
    Publication number: 20130015850
    Abstract: The cost and size of an atomic magnetometer are reduced by attaching together a first die which integrates together a vapor cell, top and side photo detectors, and processing electronics, a second die which integrates together an optics package and a heater for the vapor cell, and a third die which integrates together a VCSEL, a heater for the VCSEL, and control electronics.
    Type: Application
    Filed: July 14, 2011
    Publication date: January 17, 2013
    Inventors: Philipp Lindorfer, Peter J. Hopper, William French, Paul Mawson, Steven Hunt, Roozbeh Parsa
  • THERMALLY CONDUCTIVE SUBSTRATE FOR GALVANIC ISOLATION
    Publication number: 20130001735
    Abstract: A galvanic isolation integrated circuit system includes a semiconductor substrate; a layer of thermally conductive material, e.g., CVD nano- or poly-diamond thin film or boron nitride CVD thin film, formed over the semiconductor substrate; a first integrated circuit structure formed over the layer of thermally conductive material; a second integrated circuit structure formed over the layer of thermally conductive material, the second integrated circuit structure being spaced apart from the first integrated circuit structure; and a galvanic isolation structure formed over the layer of thermally conductive material between the first and second integrated circuit structures and connected to the first integrated circuit structure and the second integrated circuit structure.
    Type: Application
    Filed: June 28, 2011
    Publication date: January 3, 2013
    Inventors: Peter J. Hopper, William French, Ann Gabrys
  • PHOTODIODE THAT INCORPORATES A CHARGE BALANCED SET OF ALTERNATING N AND P DOPED SEMICONDUCTOR REGIONS
    Publication number: 20120326260
    Abstract: A photodiode comprises a first terminal formed in a surface of a semiconductor substrate; a second terminal formed in the substrate surface and spaced apart from the first terminal; and a plurality of adjacent alternating N-type and P-type diffusion regions formed in the substrate surface between the first terminal and the second terminal.
    Type: Application
    Filed: June 21, 2011
    Publication date: December 27, 2012
    Inventors: William French, Peter J. Hopper, Philipp Lindorfer, Vladislav Vashchenko
  • Galvanic isolation that incorporates a transformer with an optical link and that can be integrated onto a single semiconductor substrate
    Patent number: 8324603
    Abstract: Methods and structures provide galvanic isolation for electrical systems using a wide oxide filled trench, and that allows power across the system divide with a transformer, and that transmits data at a high baud rate using an optical link. The system solution allows the integration of all of these elements onto a single semiconductor substrate in contrast to currently available galvanic isolation systems that require multiple individual silicon die that are connected by wire bonds and are relatively slow.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: December 4, 2012
    Assignee: National Semiconductor Corporation
    Inventors: William French, Peter J. Hopper, Vladislav Vashchenko, Philipp Lindorfer
  • Self-propelled robotic device that moves through bodily and other passageways
    Patent number: 8303484
    Abstract: A self-propelled robotic device moves through bodily and other passageways by inflating regions of an overlying bladder along the length of the robotic device in a sequence that imparts motion to the device. The regions of the overlying bladder are inflated by energizing a plurality of coils, which are surrounded by a ferrofluid, in a sequence. The ferrofluid responds to the magnetic field created by an energized coil by creating a bulge in the side wall of the overlying bladder.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: November 6, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Philipp Lindorfer, William French, Visvamohan Yegnashankaran
  • DMOS Transistor with a Cavity that Lies Below the Drift Region
    Publication number: 20120273881
    Abstract: A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.
    Type: Application
    Filed: April 26, 2011
    Publication date: November 1, 2012
    Inventors: William French, Vladislav Vashchenko, Richard Wendell Foote, JR., Alexei Sadovnikov, Punit Bhola, Peter J. Hopper
  • DMOS Transistor with a Slanted Super Junction Drift Structure
    Publication number: 20120261753
    Abstract: A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening.
    Type: Application
    Filed: April 13, 2011
    Publication date: October 18, 2012
    Inventors: Peter J. Hopper, Alexei Sadovnikov, William French, Erika Mazotti, Richard Wendell Foote, JR., Punit Bhola, Vladislav Vashchenko
  • System and method for locating devices within a data center
    Patent number: 8285302
    Abstract: A method, computer program product, and computing system for defining a device identifier for a data center device within a data center. Location coordinates are defined for the data center device within the data center. The device identifier is associated with the location coordinates to define geospatial information for the data center device within the data center. The geospatial information is processed to locate the data center device within the data center.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: October 9, 2012
    Assignee: EMC Corporation
    Inventors: James W. Espy, F. William French
  • Power transistor with improved high-side operating characteristics and reduced resistance and related apparatus and method
    Patent number: 8274129
    Abstract: A method includes forming a transistor device on a first side of a semiconductor-on-insulator structure. The semiconductor-on-insulator structure includes a substrate, a dielectric layer, and a buried layer between the substrate and the dielectric layer. The method also includes forming a conductive plug through the semiconductor-on-insulator structure. The conductive plug is in electrical connection with the transistor device. The method further includes forming a field plate on a second side of the semiconductor-on-insulator structure, where the field plate is in electrical connection with the conductive plug. The transistor device could have a breakdown voltage of at least 600V, and the field plate could extend along at least 40% of a length of the transistor device.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: September 25, 2012
    Assignee: National Semiconductor Corporation
    Inventors: William French, Peter Smeys, Peter J. Hopper, Peter Johnson