Abstract: A computer system having two busses which are shared by one or more processors, one or more memories, one or more input/output channels and a bus control mechanism. One of the busses is used for the transmission of original messages from the processors and/or I/O channels to the memories or the bus control mechanism. The other bus is used for the transmission of reply messages by the memories or the bus control mechanism to the senders of original messages requiring a reply. The bus control mechanism includes a first control means for controlling priority and usage of the first bus and a second control means, independent of the first control means, for controlling reply message traffic over the second bus. The reply message control means is arranged to handle reply message traffic on a priority basis and a time availability basis so as to prevent hang up of the reply message bus.