Abstract: Embodiments disclosed herein provide methods of forming bond pad redistribution layers (RDLs) in a fan-out wafer level packaging (FOWLP) scheme using an additive manufacturing process. In one embodiment, a method of forming a redistribution layer includes positioning a carrier substrate on a manufacturing support of an additive manufacturing system, the carrier substrate including a plurality of singulated devices, detecting one or more fiducial features corresponding to each of the plurality of singulated devices, determining actual positions of each of the plurality of singulated devices relative to one or more components of the additive manufacturing system, generating printing instructions for forming a patterned dielectric layer based on the actual positions of each of the plurality of singulated devices, and forming the patterned dielectric layer using the printing instructions.

Abstract: Embodiments disclosed herein provide methods of forming bond pad redistribution layers (RDLs) in a fan-out wafer level packaging (FOWLP) scheme using an additive manufacturing process. In one embodiment, a method of forming a redistribution layer includes positioning a carrier substrate on a manufacturing support of an additive manufacturing system, the carrier substrate including a plurality of singulated devices, detecting one or more fiducial features corresponding to each of the plurality of singulated devices, determining actual positions of each of the plurality of singulated devices relative to one or more components of the additive manufacturing system, generating printing instructions for forming a patterned dielectric layer based on the actual positions of each of the plurality of singulated devices, and forming the patterned dielectric layer using the printing instructions.

Abstract: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.

Abstract: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.

Abstract: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.

Abstract: An apparatus for chemical mechanical polishing includes a platen having a surface to support a polishing pad, a carrier head to hold a substrate against a polishing surface of the polishing pad, a pad conditioner including a conductive body to be pressed against the polishing surface, an in-situ polishing pad thickness monitoring system including a sensor disposed in the platen to generate a magnetic field that passes through the polishing pad, and a controller configured to receive a signal from the monitoring system and generate a measure of polishing pad thickness based on a portion of the signal corresponding to a time that the sensor is below the conductive body of the pad conditioner.

Abstract: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.

Abstract: A method of controlling a polishing system includes polishing a substrate at a first polishing station, transporting the substrate to an in-line optical metrology system positioned between the first polishing station and a second polishing station, at the in-line optical metrology system measuring a spectrum reflected from the substrate, and generating a characterizing value from the spectrum, determining that the substrate needs rework based on the characterizing value, returning the substrate to the first polishing station and performing rework of the substrate at the first polishing station; and transporting the substrate to the second polishing station and polishing the substrate at the second polishing station.

Abstract: Embodiments described herein relate to removing material from a substrate. More particularly, the embodiments described herein relate to polishing or planarizing a substrate by a chemical mechanical polishing process. In one embodiment, a method of chemical mechanical polishing (CMP) of a substrate is provided. The method comprises exposing a substrate having a conductive material layer formed thereon to a polishing solution comprising phosphoric acid, one or more chelating agents, one or more corrosion inhibitors, and one or more oxidizers, forming a passivation layer on the conductive material layer, providing relative motion between the substrate and a polishing pad and removing at least a portion of the passivation layer to expose a portion of the underlying conductive material layer, and removing a portion of the exposed conductive material layer.

Abstract: A method for forming an integrated circuit is provided. In one embodiment, the method includes forming a stop layer comprising carbon doped silicon nitride on a gate region on a substrate, the gate region having a poly gate and one or more spacers formed adjacent the poly gate, forming a dielectric layer on the stop layer, and removing a portion of the dielectric layer above the gate region using a CMP process, wherein the stop layer is a strain inducing layer having a CMP removal rate that is less than the CMP removal rate of the dielectric layer and equal to or less than the CMP removal rate of the one or more spacers.

Abstract: A method and apparatus for forming an amorphous carbon layer on a substrate is provided. A first portion of the amorphous carbon layer having a high stress level is formed from a hydrocarbon precursor having high dilution ratio, with optional amine precursor included to add stress-elevating nitrogen. A second portion of the amorphous carbon layer having a low stress level is formed on the first portion by reducing the dilution ratio of the hydrocarbon precursor and lowering or eliminating the amine gas. Pressure, temperature, and RF power input may be adjusted instead of, or in addition to, precursor flow rates, and different precursors may be used for different stress levels.

Abstract: A method for forming a semiconductor structure includes forming a plurality of features across a surface of a substrate, with at least one space being between two adjacent features. A first dielectric layer is formed on the features and within the at least one space. A portion of the first dielectric layer interacts with a reactant derived from a first precursor and a second precursor to form a first solid product. The first solid product is decomposed to substantially remove the portion of the first dielectric layer. A second dielectric layer is formed to substantially fill the at least one space.

Abstract: A method for forming a semiconductor structure includes forming a plurality of features across a surface of a substrate, with at least one space being between two adjacent features. A first dielectric layer is formed on the features and within the at least one space. A portion of the first dielectric layer interacts with a reactant derived from a first precursor and a second precursor to form a first solid product. The first solid product is decomposed to substantially remove the portion of the first dielectric layer. A second dielectric layer is formed to substantially fill the at least one space.

Abstract: A method and apparatus for forming narrow vias in a substrate is provided. A pattern recess is etched into a substrate by conventional lithography. A thin conformal layer is formed over the surface of the substrate, including the sidewalls and bottom of the pattern recess. The thickness of the conformal layer reduces the effective width of the pattern recess. The conformal layer is removed from the bottom of the pattern recess by anisotropic etching to expose the substrate beneath. The substrate is then etched using the conformal layer covering the sidewalls of the pattern recess as a mask. The conformal layer is then removed using a wet etchant.

Abstract: A method for forming a semiconductor structure includes forming a plurality of features across a surface of a substrate, with at least one space being between two adjacent features. A first dielectric layer is formed on the features and within the at least one space. A portion of the first dielectric layer interacts with a reactant derived from a first precursor and a second precursor to form a first solid product. The first solid product is decomposed to substantially remove the portion of the first dielectric layer. A second dielectric layer is formed to substantially fill the at least one space.