Patents by Inventor William J. Lambert

William J. Lambert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10340260
    Abstract: An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Yongki Min, Reynaldo A. Olmedo, William J. Lambert, Kaladhar Radhakrishnan, Leigh E. Wojewoda, Venkat Anil K. Magadala, Clive R. Hendricks
  • Publication number: 20190051447
    Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.
    Type: Application
    Filed: October 17, 2018
    Publication date: February 14, 2019
    Inventors: William J. Lambert, Mihir K. Roy, Mathew J. Manusharow, Yikang Deng
  • Patent number: 10163557
    Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: William J. Lambert, Mihir K Roy, Mathew J Manusharow, Yikang Deng
  • Patent number: 10157860
    Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a stiffener on a substrate, wherein a first section of the stiffener and a second section of the stiffener are on opposite sides of an opening. At least one component may be attached on the substrate within the opening, wherein the at least one component is disposed between the first section of the stiffener and the second section of the stiffener, and wherein the stiffener comprises a grounding structure disposed on the substrate.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Kedar Dhane, Yongki Min, William J. Lambert
  • Publication number: 20180332708
    Abstract: Embodiments are generally directed to vertically embedded passive components. An embodiment of a device includes a semiconductor die; and a package coupled with the semiconductor die. The package includes one or more passive components connected with the semiconductor die, the one or more passive components being embedded vertically in the package substrate, each of the passive components including a first terminal and a second terminal. A first passive component is embedded in a through hole drilled in the package, the first terminal of the first passive component being connected to the semiconductor die by a via through an upper buildup layer on the package.
    Type: Application
    Filed: December 26, 2015
    Publication date: November 15, 2018
    Inventors: William J. LAMBERT, Mihir K. ROY, Mathew J. MANUSHAROW
  • Publication number: 20180323708
    Abstract: A printed circuit board (PCB) includes one or more voltage rails and an integrated voltage regulator (IVR) electrically coupled to supply current to a voltage rail. The PCB also includes a PCB current source electrically coupled to supply a supplementary current to the voltage rail.
    Type: Application
    Filed: December 22, 2015
    Publication date: November 8, 2018
    Inventors: William J. LAMBERT, Mathew MANUSHAROW
  • Publication number: 20180315690
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.
    Type: Application
    Filed: December 21, 2015
    Publication date: November 1, 2018
    Inventors: Adel A. ELSHERBINI, Mathew J. MANUSHAROW, Krishna BHARATH, William J. LAMBERT, Robert L. SANKMAN, Aleksandar ALEKSOV, Brandon M. RAWLINGS, Feras EID, Javier SOTO GONZALEZ, Meizi JIAO, Suddhasattwa NAD, Telesphor KAMGAING
  • Publication number: 20180197845
    Abstract: An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module.
    Type: Application
    Filed: March 5, 2018
    Publication date: July 12, 2018
    Inventors: Yongki Min, Reynaldo A. Olmedo, William J. Lambert, Kaladhar Radhakrishnan, Leigh E. Wojewoda, Venkat Anil K. Magadala, Clive R. Hendricks
  • Publication number: 20180182718
    Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a stiffener on a substrate, wherein a first section of the stiffener and a second section of the stiffener are on opposite sides of an opening. At least one component may be attached on the substrate within the opening, wherein the at least one component is disposed between the first section of the stiffener and the second section of the stiffener, and wherein the stiffener comprises a grounding structure disposed on the substrate.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 28, 2018
    Applicant: Intel Corporation
    Inventors: Omkar G. Karhade, Kedar Dhane, Yongki Min, William J. Lambert
  • Patent number: 9992871
    Abstract: Discussed generally herein are methods and devices for altering an effective series resistance (ESR) of a component. A device can include a substrate including electrical connection circuitry therein, a first via hole through a first surface of the substrate and contiguous with the electrical connection circuitry, a first conductive polymer with a resistance greater than a resistance of the electrical connection circuitry filling the first via hole, and a component electrically coupled to the first conductive polymer.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: William J. Lambert, Mathew J Manusharow
  • Publication number: 20180101207
    Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.
    Type: Application
    Filed: September 5, 2017
    Publication date: April 12, 2018
    Inventors: Krishna Bharath, Srikrishnan Venkataraman, William J. Lambert, Michael J. Hill, Alexander Slepoy, Dong Zhong, Kaladhar Radhakrishnan, Hector A. Aguirre Diaz, Jonathan P. Douglas
  • Patent number: 9911723
    Abstract: An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: March 6, 2018
    Assignee: Intel Corporation
    Inventors: Yongki Min, Reynaldo A. Olmedo, William J. Lambert, Kaladhar Radhakrishnan, Leigh E. Wojewoda, Venkat Anil K. Magadala, Clive R. Hendricks
  • Patent number: 9899311
    Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: February 20, 2018
    Assignee: Intel Corporation
    Inventors: Mathew J. Manusharow, Daniel N. Sobieski, Mihir K. Roy, William J. Lambert
  • Patent number: 9842832
    Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: December 12, 2017
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, John S. Guzek, Johanna M. Swan, Christopher J. Nelson, Nitin A. Deshpande, William J. Lambert, Charles A. Gealer, Feras Eid, Islam A. Salama, Kemal Aygun, Sasha N. Oster, Tyler N. Osborn
  • Patent number: 9753510
    Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: September 5, 2017
    Assignee: Intel Corporation
    Inventors: Krishna Bharath, Srikrishnan Venkataraman, William J. Lambert, Michael J. Hill, Alexander Slepoy, Dong Zhong, Kaladhar Radhakrishnan, Hector A. Aguirre Diaz, Jonathan P. Douglas
  • Publication number: 20170178786
    Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.
    Type: Application
    Filed: December 17, 2015
    Publication date: June 22, 2017
    Inventors: William J. Lambert, Mihir K. Roy, Mathew J. Manusharow, Yikang Deng
  • Publication number: 20170179094
    Abstract: An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: Yongki Min, Reynaldo A. Olmedo, William J. Lambert, Kaladhar Radhakrishnan, Leigh E. Wojewoda, Venkat Anil K. Magadala, Clive R. Hendricks
  • Publication number: 20170169932
    Abstract: Apparatus and methods are provided for a wire based inductor component. In an example, an inductor apparatus can include a wire and a plurality of individual layers of magnetic material surrounding the wire.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 15, 2017
    Inventors: William J. Lambert, Kevin O'Brien, Omkar Karhade
  • Publication number: 20170135211
    Abstract: Discussed generally herein are methods and devices for altering an effective series resistance (ESR) of a component. A device can include a substrate including electrical connection circuitry therein, a first via hole through a first surface of the substrate and contiguous with the electrical connection circuitry, a first conductive polymer with a resistance greater than a resistance of the electrical connection circuitry filling the first via hole, and a component electrically coupled to the first conductive polymer.
    Type: Application
    Filed: November 10, 2015
    Publication date: May 11, 2017
    Inventors: William J. Lambert, Mathew J. Manusharow
  • Patent number: 9633938
    Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Mathew J. Manusharow, Daniel N. Sobieski, Mihir K. Roy, William J. Lambert