Abstract: A radio receiver (300) having a multi-state variable threshold automatic gain control (AGC) for fast channel scanning acquisition includes an amplifier (303) having an automatic gain control (AGC) for controlling the gain of a receiver analog signal. An analog-to-digital converter (ADC) (311) is used for converting the receiving analog signal to a digital signal while a digital signal processor (DSP) (325) operates to process the digital signal. A signal magnitude estimator (315) in an AGC controller (313) provides a signal strength estimate of the received signal. The AGC controller (313) then sets the receiver amplifier (303) for an open-loop AGC operational mode and sets a first threshold for triggering an interrupt service request (ISR). This ISR is provided the DSP (325) and the host processor (327) if a radio frequency (RF) signal is detected above a first threshold during a priority scan of a priority channel to minimize interruptions in audio during priority scan.

Abstract: A radio receiver (300) having a multi-state variable threshold automatic gain control (AGC) for fast channel scanning acquisition includes an amplifier (303) having an automatic gain control (AGC) for controlling the gain of a receiver analog signal. An analog-to-digital converter (ADC) (311) is used for converting the receiving analog signal to a digital signal while a digital signal processor (DSP) (325) operates to process the digital signal. A signal magnitude estimator (315) in an AGC controller (313) provides a signal strength estimate of the received signal. The AGC controller (313) then sets the receiver amplifier (303) for an open-loop AGC operational mode and sets a first threshold for triggering an interrupt service request (ISR). This ISR is provided the DSP (325) and the host processor (327) if a radio frequency (RF) signal is detected above a first threshold during a priority scan of a priority channel to minimize interruptions in audio during priority scan.

Abstract: A method and apparatus for a pulse width modulated (PWM) signal (30, 130) is provided. The input is a digital signal which is a modulated signal (24, 124). In the illustrated form, the modulated input signal is either a PDM signal or a PCM signal. In one embodiment of the present invention a PCM to PWM converter (16, 116) includes correction of duty ratio circuitry (48). The methodology used may include recursion on the values obtained after prediction, interpolation, and correction. The digital to analog conversion system (10) uses a PDM to PWM converter (20) which operates in an all digital domain and includes no analog circuitry.

Abstract: A method and apparatus for a pulse width modulated (PWM) signal (30, 130) is provided. The input is a digital signal which is a modulated signal (24, 124). In the illustrated form, the modulated input signal is either a PDM signal or a PCM signal. In one embodiment of the present invention a PCM to PWM converter (16, 116) includes correction of duty ratio circuitry (48). The methodology used may include recursion on the values obtained after prediction, interpolation, and correction. The digital to analog conversion system (10) uses a PDM to PWM converter (20) which operates in an all digital domain and includes no analog circuitry.

Abstract: A method for performing timing synchronization between digital input data and a system clock in a communication device includes providing a system clock rate that is higher than a data clock rate and sampling the input data at intervals in the system clock periods within the data clock period. The method includes adjusting the timing between the digital input data and the system clock by either shortening the number of system clock periods and sampling intervals, or lengthening the number of system clock periods and sampling the input data at normal intervals and providing data insertion to fill one of the extra system clock periods, such that more data samples are provided in the data clock period.