Patents by Inventor William J. Starke
William J. Starke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230118362Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.Type: ApplicationFiled: December 19, 2022Publication date: April 20, 2023Inventors: Charles F. Marino, William J. Starke, Praveen S. Reddy, John T. Hollaway, JR., Daniel C. Howe, David J. Krolak
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Publication number: 20230061266Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Charles F. Marino, William J. Starke, Praveen S. Reddy, John T. Hollaway, JR., Daniel C. Howe, David J. Krolak
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Patent number: 11580058Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.Type: GrantFiled: August 30, 2021Date of Patent: February 14, 2023Assignee: International Business Machines CorporationInventors: Charles F. Marino, William J. Starke, Praveen S. Reddy, John T. Hollaway, Jr., Daniel C. Howe, David J. Krolak
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Patent number: 11573896Abstract: A method, system, and computer program product for local DRAM caching of storage class memory elements are provided. The method identifies a cache line with a cache address in a local dynamic random-access memory (DRAM). The cache line is compressed within the local DRAM to generate a compressed cache line and an open memory space within the local DRAM. A cache tag is generated in the open memory space and a validation value is generated in the open memory space for the compressed cache line. The method determines a cache-hit for the cache line based on the cache address, the cache tag, and the validation value.Type: GrantFiled: June 25, 2021Date of Patent: February 7, 2023Assignee: International Business Machines CorporationInventors: Bulent Abali, Bartholomew Blaner, Alper Buyuktosunoglu, William J. Starke
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Publication number: 20230036054Abstract: A destination host includes a processor core, a system fabric, a memory system, and a link controller communicatively coupled to the system fabric and configured to be communicatively coupled, via a communication link, to a source host with which the destination host is non-coherent. The destination host migrates, via the communication link, a state of a logical partition from the source host to the destination host and page table entries for translating addresses of a dataset of the logical partition from the source host to the destination host. After migrating the state and page table entries, the destination host initiates execution of the logical partition on the processor core while at least a portion of the dataset of the logical partition resides in the memory system of the source host and migrates, via the communication link, the dataset of the logical partition to the memory system of the destination host.Type: ApplicationFiled: July 29, 2021Publication date: February 2, 2023Inventors: DEREK E. WILLIAMS, GUY L. GUTHRIE, William J. Starke, Jeffrey A. Stuecheli
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Publication number: 20220414007Abstract: A method, system, and computer program product for local DRAM caching of storage class memory elements are provided. The method identifies a cache line with a cache address in a local dynamic random-access memory (DRAM). The cache line is compressed within the local DRAM to generate a compressed cache line and an open memory space within the local DRAM. A cache tag is generated in the open memory space and a validation value is generated in the open memory space for the compressed cache line. The method determines a cache-hit for the cache line based on the cache address, the cache tag, and the validation value.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Inventors: Bulent Abali, Bartholomew Blaner, Alper Buyuktosunoglu, William J. Starke
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Patent number: 11341060Abstract: In a data processing environment, a communication interface of a second host data processing system receives, from a first host data processing system, a host command in a first command set. The host command specifies a memory access to a memory coupled to the second host data processing system. The communication interface translates the host command into a command in a different second command set emulating coupling of an attached functional unit to the communication interface. The communication interface presents the second command to a host bus protocol interface of the second host data processing system. Based on receipt of the second command, the host bus protocol interface initiates, on a system fabric of the second host data processing system, a host bus protocol memory access request specifying the memory access.Type: GrantFiled: August 11, 2020Date of Patent: May 24, 2022Assignee: International Business Machines CorporationInventors: Michael S. Siegel, William J. Starke, Jeffrey A. Stuecheli, Lakshminarayana Arimilli, Kenneth M. Valk, James Mikos, David Krolak
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Patent number: 11281582Abstract: A data processing system includes multiple processing units all having access to a shared memory system. A processing unit includes a lower level cache configured to serve as a point of systemwide coherency and a processor core coupled to the lower level cache. The processor core includes an upper level cache, an execution unit that executes a store-conditional instruction to generate a store-conditional request that specifies a store target address and store data, and a flag that, when set, indicates the store-conditional request can be completed early in the processor core. The processor core also includes completion logic configured to commit an update of the shared memory system with the store data specified by the store-conditional request based on whether the flag is set.Type: GrantFiled: January 14, 2020Date of Patent: March 22, 2022Assignee: International Business Machines CorporationInventors: Derek E. Williams, Guy L. Guthrie, William J. Starke, Hugh Shen
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Patent number: 11269561Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.Type: GrantFiled: December 21, 2020Date of Patent: March 8, 2022Assignee: International Business Machines CorporationInventors: Jie Zheng, Steven R. Carlough, William J. Starke, Jeffrey A. Stuecheli, Stephen J. Powell
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Publication number: 20220050787Abstract: In a data processing environment, a communication interface of a second host data processing system receives, from a first host data processing system, a host command in a first command set. The host command specifies a memory access to a memory coupled to the second host data processing system. The communication interface translates the host command into a command in a different second command set emulating coupling of an attached functional unit to the communication interface. The communication interface presents the second command to a host bus protocol interface of the second host data processing system. Based on receipt of the second command, the host bus protocol interface initiates, on a system fabric of the second host data processing system, a host bus protocol memory access request specifying the memory access.Type: ApplicationFiled: August 11, 2020Publication date: February 17, 2022Inventors: Michael S. Siegel, William J. Starke, Jeffrey A. Stuecheli, Lakshminarayana Arimilli, Kenneth M. Valk, James Mikos, David Krolak
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Patent number: 11157411Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.Type: GrantFiled: November 22, 2019Date of Patent: October 26, 2021Assignee: International Business Machines CorporationInventors: Sanjeev Ghai, Guy L. Guthrie, Stephen J. Powell, William J. Starke
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Patent number: 11113204Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an accelerator functional unit and an effective address-based accelerator cache for buffering copies of data from the system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory.Type: GrantFiled: April 18, 2019Date of Patent: September 7, 2021Assignee: International Business Machines CorporationInventors: Bartholomew Blaner, Michael S. Siegel, Jeffrey A. Stuecheli, William J. Starke, Kenneth M. Valk, John D. Irish, Lakshminarayana Arimilli
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Patent number: 11074205Abstract: A snooper of a processing unit connected to processing units via a system fabric receives a first single bus command in a bus protocol that allows sampling over the system fabric of the capability of snoopers to handle an interrupt and returns a first response indicating the capability of the snooper to handle the interrupt. The snooper, in response to receiving a second single bus command in the bus protocol to poll a first selection of snoopers for an availability status to service a criteria specified in the second single bus command, returns a second response indicating the availability of the snooper to service the criteria. The snooper, in response to receiving a third single bus command in the bus protocol to direct the snooper to handle the interrupt, assigns the interrupt to a particular processor thread of a respective selection of the one or more separate selections of processors threads distributed in the processing unit.Type: GrantFiled: August 14, 2019Date of Patent: July 27, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard L. Arndt, Florian Auernhammer, Wayne M. Barrett, Robert A. Drehmel, Guy L. Guthrie, Michael S. Siegel, William J. Starke
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Publication number: 20210216457Abstract: A data processing system includes multiple processing units all having access to a shared memory system. A processing unit includes a lower level cache configured to serve as a point of systemwide coherency and a processor core coupled to the lower level cache. The processor core includes an upper level cache, an execution unit that executes a store-conditional instruction to generate a store-conditional request that specifies a store target address and store data, and a flag that, when set, indicates the store-conditional request can be completed early in the processor core. The processor core also includes completion logic configured to commit an update of the shared memory system with the store data specified by the store-conditional request based on whether the flag is set.Type: ApplicationFiled: January 14, 2020Publication date: July 15, 2021Inventors: DEREK E. WILLIAMS, GUY L. GUTHRIE, WILLIAM J. STARKE, HUGH SHEN
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Patent number: 11042325Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.Type: GrantFiled: August 5, 2019Date of Patent: June 22, 2021Assignee: International Business Machines CorporationInventors: Jie Zheng, Steven R. Carlough, William J. Starke, Jeffrey A. Stuecheli, Stephen J. Powell
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Patent number: 11030110Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes request logic that communicates memory access requests and request responses with the accelerator unit.Type: GrantFiled: April 26, 2019Date of Patent: June 8, 2021Assignee: International Business Machines CorporationInventors: Michael S. Siegel, Bartholomew Blaner, Jeffrey A. Stuecheli, William J. Starke, Derek E. Williams, Kenneth M. Valk, John D. Irish, Lakshminarayana Arimilli
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Patent number: 10991635Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips.Type: GrantFiled: July 20, 2019Date of Patent: April 27, 2021Assignee: International Business Machines CorporationInventors: Dale Curtis McHerron, Kamal K. Sikka, Joshua M. Rubin, Ravi K. Bonam, Ramachandra Divakaruni, William J. Starke, Maryse Cournoyer
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Publication number: 20210109680Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.Type: ApplicationFiled: December 21, 2020Publication date: April 15, 2021Inventors: Jie ZHENG, Steven R. CARLOUGH, William J. STARKE, Jeffrey A. STUECHELI, Stephen J. POWELL
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Publication number: 20210042058Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.Type: ApplicationFiled: August 5, 2019Publication date: February 11, 2021Applicants: International Business Machines Corporation, International Business Machines CorporationInventors: Jie ZHENG, Steven R. CARLOUGH, William J. STARKE, Jeffrey A. STUECHELI, Stephen J. POWELL
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Publication number: 20210020529Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips.Type: ApplicationFiled: July 20, 2019Publication date: January 21, 2021Inventors: Dale Curtis McHerron, Kamal K. Sikka, Joshua M. Rubin, Ravi K. Bonam, Ramachandra Divakaruni, William J. Starke, Maryse Courmoyer