Patents by Inventor William K. Henson
William K. Henson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170170016Abstract: Methods for multiple patterning a substrate may include: forming a hard mask including a carbonaceous layer and an oxynitride layer over the carbonaceous layer on a substrate; and forming a first pattern into the oxynitride layer and partially into the carbonaceous layer using a first soft mask positioned over the hard mask. A wet etching removes a portion of the first soft mask from the first pattern in the oxynitride layer without damaging the carbonaceous layer. Subsequently, a second pattern and a third pattern are formed into the hard mask, creating a multiple pattern in the hard mask. The multiple pattern may be etched into the substrate, followed by removing any remaining portion of the hard mask.Type: ApplicationFiled: December 14, 2015Publication date: June 15, 2017Inventors: Woo-Hyeong Lee, Jujin An, Shahrukh A. Khan, Rosa A. Orozco-Teran, Oluwafemi O. Ogunsola, William K. Henson, Scott R. Stiffler
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Patent number: 9252146Abstract: A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.Type: GrantFiled: May 19, 2014Date of Patent: February 2, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yue Liang, Dechao Guo, William K. Henson, Shreesh Narasimha, Yanfeng Wang
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Patent number: 9082877Abstract: A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.Type: GrantFiled: May 30, 2014Date of Patent: July 14, 2015Assignee: International Business Machines CorporationInventors: Yue Liang, Dureseti Chidambarrao, Brian J. Greene, William K. Henson, Unoh Kwon, Shreesh Narasimha, Xiaojun Yu
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Patent number: 9040399Abstract: A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.Type: GrantFiled: October 27, 2011Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: MaryJane Brodsky, Ming Cai, Dechao Guo, William K. Henson, Shreesh Narasimha, Yue Liang, Liyang Song, Yanfeng Wang, Chun-Chen Yeh
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Patent number: 8962417Abstract: A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source/drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed.Type: GrantFiled: March 15, 2013Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: Kern Rim, William K. Henson, Yue Liang, Xinlin Wang
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Patent number: 8946721Abstract: A method is provided that includes forming a high-k dielectric etch stop layer over at least a first conductivity type semiconductor device on a first portion of a substrate and at least a second conductivity type semiconductor device on a second portion of the semiconductor device. A first stress-inducing layer is deposited over the first conductivity type semiconductor device and the second conductivity type semiconductor device. The portion of the first stress-inducing layer that is formed over the second conductivity type semiconductor device is then removed with an etch that is selective to the high-k dielectric etch stop layer to provide an exposed surface of second portion of the substrates that includes at least the second conductivity type semiconductor device. A second stress-inducing layer is then formed over the second conductivity type semiconductor device.Type: GrantFiled: February 28, 2013Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventor: William K. Henson
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Publication number: 20140349451Abstract: A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.Type: ApplicationFiled: May 30, 2014Publication date: November 27, 2014Applicant: International Business Machines CorporationInventors: Yue Liang, Dureseti Chidambarrao, Brian J. Greene, William K. Henson, Unoh Kwon, Shreesh Narasimha, Xiaojun Yu
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Publication number: 20140273381Abstract: A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source/drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kern Rim, William K. Henson, Yue Liang, Xinlin Wang
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Publication number: 20140246727Abstract: A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.Type: ApplicationFiled: May 19, 2014Publication date: September 4, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yue Liang, Dechao Guo, William K. Henson, Shreesh Narasimha, Yanfeng Wang
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Patent number: 8803243Abstract: A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.Type: GrantFiled: January 3, 2012Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Yue Liang, Dureseti Chidambarrao, Brian J. Greene, William K. Henson, Unoh Kwon, Shreesh Narasimha, Xiaojun Yu
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Patent number: 8729637Abstract: A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.Type: GrantFiled: October 5, 2011Date of Patent: May 20, 2014Assignee: International Business Machines CorporationInventors: Yue Liang, Dechao Guo, William K. Henson, Shreesh Narasimha, Yanfeng Wang
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Patent number: 8728925Abstract: Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated.Type: GrantFiled: May 3, 2012Date of Patent: May 20, 2014Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, William K. Henson, Unoh Kwon
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Patent number: 8673757Abstract: A method is provided that includes forming a high-k dielectric etch stop layer over at least a first conductivity type semiconductor device on a first portion of a substrate and at least a second conductivity type semiconductor device on a second portion of the semiconductor device. A first stress-inducing layer is deposited over the first conductivity type semiconductor device and the second conductivity type semiconductor device. The portion of the first stress-inducing layer that is formed over the second conductivity type semiconductor device is then removed with an etch that is selective to the high-k dielectric etch stop layer to provide an exposed surface of second portion of the substrates that includes at least the second conductivity type semiconductor device. A second stress-inducing layer is then formed over the second conductivity type semiconductor device.Type: GrantFiled: October 28, 2010Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventor: William K. Henson
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Patent number: 8659054Abstract: A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source region and the drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided in this disclosure by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is thus provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed.Type: GrantFiled: October 15, 2010Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: Kern Rim, William K. Henson, Yue Liang, Xinlin Wang
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Patent number: 8598009Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.Type: GrantFiled: April 26, 2012Date of Patent: December 3, 2013Assignees: International Business Machines Corporation, Globalfoundries, Inc.Inventors: Brian J. Greene, William K. Henson, Judson R. Holt, Michael D. Steigerwalt, Kuldeep Amarnath, Rohit Pal, Johan W. Weijtmans
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Patent number: 8575709Abstract: Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.Type: GrantFiled: July 24, 2012Date of Patent: November 5, 2013Assignee: International Business Machines CorporationInventors: Huiming Bu, Michael P. Chudzik, Wei He, William K. Henson, Siddarth A. Krishnan, Unoh Kwon, Naim Moumen, Wesley C. Natzle
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Patent number: 8507992Abstract: A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.Type: GrantFiled: March 15, 2011Date of Patent: August 13, 2013Assignee: International Business Machines CorporationInventors: Renee T. Mo, Huiming Bu, Michael P. Chudzik, William K. Henson, Mukesh V. Khare, Vijay Narayanan
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Publication number: 20130168776Abstract: A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.Type: ApplicationFiled: January 3, 2012Publication date: July 4, 2013Applicant: International Business Machines CorporationInventors: Yue Liang, Dureseti Chidambarrao, Brian J. Greene, William K. Henson, Unoh Kwon, Shreesh Narasimha, Xiaojun Yu
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Publication number: 20130105894Abstract: A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.Type: ApplicationFiled: October 27, 2011Publication date: May 2, 2013Applicant: International Business Machines CorporationInventors: MaryJane Brodsky, Ming Cai, Dechao Guo, William K. Henson, Shreesh Narasimha, Yue Liang, Liyang Song, Yanfeng Wang, Chun-Chen Yeh
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Publication number: 20130105896Abstract: A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor.Type: ApplicationFiled: September 24, 2012Publication date: May 2, 2013Applicant: International Business Machines CorporationInventors: MaryJane Brodsky, Ming Cai, Dechao Guo, William K. Henson, Shreesh Narasimha, Yue Liang, Liyang Song, Yanfeng Wang, Chun-Chen Yeh