Patents by Inventor William K. Lewchuk

William K. Lewchuk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8589629
    Abstract: A system and method for data allocation in a shared cache memory of a computing system are contemplated. Each cache way of a shared set-associative cache is accessible to multiple sources, such as one or more processor cores, a graphics processing unit (GPU), an input/output (I/O) device, or multiple different software threads. A shared cache controller enables or disables access separately to each of the cache ways based upon the corresponding source of a received memory request. One or more configuration and status registers (CSRs) store encoded values used to alter accessibility to each of the shared cache ways. The control of the accessibility of the shared cache ways via altering stored values in the CSRs may be used to create a pseudo-RAM structure within the shared cache and to progressively reduce the size of the shared cache during a power-down sequence while the shared cache continues operation.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: November 19, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jonathan Owen, Guhan Krishnan, Carl D. Dietz, Douglas Richard Beard, William K. Lewchuk, Alexander Branover
  • Publication number: 20100250856
    Abstract: A system and method for data allocation in a shared cache memory of a computing system are contemplated. Each cache way of a shared set-associative cache is accessible to multiple sources, such as one or more processor cores, a graphics processing unit (GPU), an input/output (I/O) device, or multiple different software threads. A shared cache controller enables or disables access separately to each of the cache ways based upon the corresponding source of a received memory request. One or more configuration and status registers (CSRs) store encoded values used to alter accessibility to each of the shared cache ways. The control of the accessibility of the shared cache ways via altering stored values in the CSRs may be used to create a pseudo-RAM structure within the shared cache and to progressively reduce the size of the shared cache during a power-down sequence while the shared cache continues operation.
    Type: Application
    Filed: March 27, 2009
    Publication date: September 30, 2010
    Inventors: Jonathan Owen, Guhan Krishnan, Carl D. Dietz, Douglas Richard Beard, William K. Lewchuk, Alexander Branover
  • Patent number: 6446189
    Abstract: A processor is presented including a cache unit coupled to a bus interface unit (BIU). Address signal selection and masking functions are performed by circuitry within the BIU rather than within the cache unit, and physical addresses produced by the BIU are stored within the TLB. As a result, address signal selection and masking circuitry (e.g., a multiplexer and gating logic) are eliminated from a critical speed path within the cache unit, allowing the operational speed of the cache unit to be increased. The cache unit stores data items, and produces a data item corresponding to a received linear address. A translation lookaside buffer (TLB) within the cache unit stores multiple linear addresses and corresponding physical addresses. When a physical address corresponding to the received linear address is not found within the TLB, the cache unit passes the linear address to the BIU.
    Type: Grant
    Filed: June 1, 1999
    Date of Patent: September 3, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gerald D. Zuraski, Jr., Frederick D. Weber, William A. Hughes, William K. Lewchuk, Scott A. White, Michael T. Clark
  • Patent number: 6430639
    Abstract: A system and method for using a toggle command for setting and releasing a lock, i.e. a locktoggle. In an exemplary computer system, one or more processors are each coupled to a bus bridge through separate high speed connections, such as a pair of uni-directional address buses with respective source-synchronous clock lines and a bi-directional data bus with attendant source-synchronous clock lines. The locktoggle command is used to transmit both a lock request and an unlock request from a processor to a system coherency. point, e.g. the bus bridge. The system coherency point acknowledges when the lock has been established or released. While the lock is active, other processors are inhibited. from accessing at least the memory locations for which the lock was initiated. Locks are thus established at the system coherency point, which may advantageously allow for locking functionality in a non-shared bus system.
    Type: Grant
    Filed: June 23, 1999
    Date of Patent: August 6, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Derrick R. Meyer, William K. Lewchuk
  • Patent number: 5608878
    Abstract: A multiprocessing system utilizes a bus protocol having two response windows. The first response window is at a fixed latency from the transmission of a bus request and/or address, while the second response window, utilized for coherency reporting, is placed a configurable number of clock cycles after the bus request and address to allow for longer access, or snoop, times to perform a cache directory look-up within other bus devices. The first response window reports error or flow control and error status. Furthermore, a method had been described, which implements the reporting of response information in a flexible and high performance manner.
    Type: Grant
    Filed: October 3, 1994
    Date of Patent: March 4, 1997
    Assignees: International Business Machines Corporation, Motorola, Inc.
    Inventors: Ravi K. Arimilli, John M. Kaiser, William K. Lewchuk, Michael S. Allen