Abstract: An I/O controller for transferring data between a host processor and one or more I/O devices. This I/O controller includes a microprocessor, a direct memory access controller and a dual port storage unit, one port of which is coupled to the host processor I/O channel bus and the other port of which is coupled to the microprocessor bus. All data transfers are by way of the dual port storage unit. The I/O controller includes an interleaving mechanism for enabling concurrent performance of two different modes of data transfer between the host processor and the I/O controller. In particular, this interleaving mechanism enables host processor direct program control (DPC) data transfers to be performed at the same time that the I/O controller is busy doing cycle steal data transfers for a block of data. These DPC data transfers are accomplished without interrupting the cycle stealing operations.

Abstract: There is disclosed herein printer control logic for controlling a matrix printer. The control logic includes an interruptable microprocessor, together with associated memory. Additionally the control logic includes a programmable timer which provides a signal a determined time after being programmed. The control logic responds to print emitter signals manifesting an incremental movement of the print head by interrupting the microprocessor. The microprocessor then programs the timer to provide signals after a programmed delay time to again interrupt the microprocessor. The microprocessor then provides signals causing the operation of the print elements on print head.