Abstract: Methods and systems are provided for managing a GUI of a web browser. When a user interaction with a tab presentation control is detected, a horizontal tab strip having first navigation tab controls for a set of webpages is removed, and a vertical tab strip having second navigation tab controls for the same set of webpages is displayed in a vertical column in the browser. In response to detecting a user hover interaction with the vertical tab strip while the vertical tab strip is in a collapsed state, the vertical tab strip is expanded from the collapsed state to an expanded state. In response to termination of the user hover interaction, the vertical tab strip is collapsed from the expanded state to the collapsed state. The vertical tab strip in the collapsed state occupies a smaller portion of the GUI then the vertical tab strip in the expanded state.

Abstract: An apparatus and method for loop flattening and reduction in a SIMD pipeline including broadcast, move, and reduction instructions.

Abstract: Disclosed embodiments relate to a new instruction for performing data-ready memory access operations.

Abstract: Disclosed embodiments relate to a new instruction for performing data-ready memory access operations.

Abstract: Disclosed embodiments relate to a new instruction for performing data-ready memory access operations. In one example, a system includes circuits to fetch, decode, and execute an instruction that includes an opcode, at least one memory location identifier identifying at least one data element, a register identifier, a data readiness indicator identifying at least one data access condition, and a data readiness mask, wherein the execution circuit is to, for each data element of the at least one data element, determine whether a memory request for the data element satisfies the at least one data access condition identified by the data readiness indicator, and in response to determining that the data access condition: generate a prefetch request for the data element, and set a value in a corresponding data element position of the data readiness mask to indicate that the memory request for the data element does not satisfy the at least one data access condition.

Abstract: An apparatus and method for loop flattening and reduction in a SIMD pipeline including broadcast, move, and reduction instructions.

Abstract: An apparatus and method for loop flattening and reduction in a SIMD pipeline including broadcast, move, and reduction instructions. One embodiment of a processor comprises: a decoder to decode a broadcast instruction to generate a decoded broadcast instruction identifying a plurality of operations, the broadcast instruction including an opcode and first and second source operands, and having a split value associated therewith; and execution circuitry to execute the operations of the decoded broadcast instruction to copy a first data element specified by the first source operand to each of a first set of contiguous data element locations in a destination register and to copy a second data element specified by the second source operand to a second set of contiguous data element locations in the destination register, wherein the first and second sets of contiguous data element locations are determined in accordance with the split value.

Abstract: Systems, methods, and apparatuses for executing an instruction are described. In some embodiments, the instruction includes at least an opcode, a field for a packed data source operand, and a field for a packed data destination operand. When executed, the instruction causes for each data element position of the source operand, multiply to a value stored in that data element position all values stored in preceding data element positions of the packed data source operand and store a result of the multiplication into a corresponding data element position of the packed data destination operand.

Abstract: Disclosed embodiments relate to instructions for dual-destination type conversion, accumulation, and atomic memory operations. In one example, a system includes a memory, a processor including: a fetch circuit to fetch the instruction from a code storage, the instruction including an opcode, a first destination identifier, and a source identifier to specify a source vector register, the source vector register including a plurality of single precision floating point data elements, a decode circuit to decode the fetched instruction, and an execution circuit to execute the decoded instruction to: convert the elements of the source vector register into double precision floating point values, store a first half of the double precision floating point values to a first location identified by the first destination identifier, and store a second half of the double precision floating point values to a second location.

Abstract: Disclosed embodiments relate to a new instruction for performing data-ready memory access operations. In one example, a system includes circuits to fetch, decode, and execute an instruction that includes an opcode, at least one memory location identifier identifying at least one data element, a register identifier, a data readiness indicator identifying at least one data access condition, and a data readiness mask, wherein the execution circuit is to, for each data element of the at least one data element, determine whether a memory request for the data element satisfies the at least one data access condition identified by the data readiness indicator, and in response to determining that the data access condition: generate a prefetch request for the data element, and set a value in a corresponding data element position of the data readiness mask to indicate that the memory request for the data element does not satisfy the at least one data access condition.

Abstract: An apparatus and method for loop flattening and reduction in a SIMD pipeline including broadcast, move, and reduction instructions.

Abstract: An apparatus and method for loop flattening and reduction in a SIMD pipeline including broadcast, move, and reduction instructions.

Abstract: An apparatus and method for loop flattening and reduction in a SIMD pipeline including broadcast, move, and reduction instructions.

Abstract: Systems, methods, and apparatuses for executing an instruction are described. For example, an instruction includes at least an opcode, a field for a packed data source operand, and a field for a packed data destination operand. When executed, the instruction causes for each data element position of the source operand, add to a value stored in that data element position all values stored in preceding data element positions of the packed data source operand and store a result of the addition into a corresponding data element position of the packed data destination operand.

Abstract: Systems, methods, and apparatuses for executing an instruction are described. In some embodiments, the instruction includes at least an opcode, a field for a packed data source operand, and a field for a packed data destination operand. When executed, the instruction causes for each data element position of the source operand, multiply to a value stored in that data element position all values stored in preceding data element positions of the packed data source operand and store a result of the multiplication into a corresponding data element position of the packed data destination operand.

Abstract: Disclosed embodiments relate to instructions for dual-destination type conversion, accumulation, and atomic memory operations. In one example, a system includes a memory, a processor including: a fetch circuit to fetch the instruction from a code storage, the instruction including an opcode, a first destination identifier, and a source identifier to specify a source vector register, the source vector register including a plurality of single precision floating point data elements, a decode circuit to decode the fetched instruction, and an execution circuit to execute the decoded instruction to: convert the elements of the source vector register into double precision floating point values, store a first half of the double precision floating point values to a first location identified by the first destination identifier, and store a second half of the double precision floating point values to a second location.

Abstract: Systems, methods, and apparatuses for executing an instruction are described. In some embodiments, the instruction includes at least an opcode, a field for a packed data source operand, and a field for a packed data destination operand. When executed, the instruction causes for each data element position of the source operand, multiply to a value stored in that data element position all values stored in preceding data element positions of the packed data source operand and store a result of the multiplication into a corresponding data element position of the packed data destination operand.

Abstract: Systems, methods, and apparatuses for executing an instruction are described. In some embodiments, the instruction includes at least an opcode, a field for a packed data source operand, and a field for a packed data destination operand. When executed, the instruction causes for each data element position of the source operand, multiply to a value stored in that data element position all values stored in preceding data element positions of the packed data source operand and store a result of the multiplication into a corresponding data element position of the packed data destination operand.

Abstract: Systems, methods, and apparatuses for executing an instruction are described. For example, an instruction includes at least an opcode, a field for a packed data source operand, and a field for a packed data destination operand. When executed, the instruction causes for each data element position of the source operand, add to a value stored in that data element position all values stored in preceding data element positions of the packed data source operand and store a result of the addition into a corresponding data element position of the packed data destination operand.

Abstract: In one embodiment, a processor includes: a fetch logic to fetch instructions, the instructions including a partial reduction instruction; a decode logic to decode the partial reduction instruction and provide the decoded partial reduction instruction to one or more execution units; and the one or more execution units to, responsive to the decoded partial reduction instruction, perform a plurality of N partial reduction operations to generate an result array including N output data elements, where an input array comprises N lanes, and where each of the N partial reduction operations is to reduce a set of input data elements included in a corresponding lane of the N lanes. Other embodiments are described and claimed.