Abstract: A wireless local area network (LAN) for data communications. The wireless LAN includes a packet hopping access terminal (PHAST) and a packet hopping gateway (PHG). The PHAST has a first transceiver for wirelessly communicating with a client device, and a second transceiver for wirelessly receiving data packets addressed to the client device and for wirelessly transmitting data packets received from the client device in accordance with a packet hopping protocol. The PHG has a transceiver for wirelessly receiving the data packets transmitted by the PHAST and for transmitting the data packets addressed to the client device in accordance with the packet hopping protocol, and a network interface for establishing communication with a server.

Abstract: A reduced cost digital data modulation and demodulation scheme for very small aperture terminal (VSAT) satellite communication systems combines non-coherent frequency detection with trellis-coded, multi-frequency modulation. The technique is robust to phase noise and frequency uncertainty and is capable of achieving the performance of rate one-half phase shift keyed modulation. The code width of data to be transmitted bears a prescribed relationship to the size of a multiple frequency set and the selection of a given combination of frequencies within that set for transmission during a respective baud. One portion the data is convolutionally encoded and provides a pointer to one of plural groups of orthogonal signal sets associated with frequencies into which the multiple frequency set has been partitioned. Another portion of the data identifies the frequency combination within the group pointed to by the one portion. The combined portions encode a multi-frequency waveform transmitted to the receiver site.

Abstract: A reduced cost, robust data communication scheme for very small aperture terminal satellite communication systems combines non-coherent frequency detection and trellis-coded, multi-frequency modulation. The data code width is associated with the size of a multiple frequency set and the selection of a given combination of frequencies for transmission during a respective baud. One portion the data is convolutionally encoded and points to an orthogonal signal set associated with frequencies of a partitioned multiple frequency set. Another portion of the data identifies the frequency combination within the group pointed to by the one portion. The combined portions encode a multi-frequency transmission waveform. At the receiver, the multi-frequency tone sequence is detected by non-coherent frequency detection. For each baud, matched filters output a most likely set of frequencies transmitted during that baud, as soft decisions to a Viterbi decoder.

Abstract: An adaptive bit synchronizer is operable to extract digital data and its associated clock from a transmitted digital signal, and includes a tunable matched filter set for modifying the input signal to correct for deviations in offset and gain, which filter set includes data, transition and derivative matched filters. A sampling device samples the output of the data matched filter for making bit decision and for estimating the reliability thereof. A clock-producing device is connected with the matched filter set for producing at least two clocks, use being made of an optimum phase detector for estimating the time error between the proper clock edge and the actual clock edges. A loop filter circuit smooths the estimates of the proper clock time to generate clock signals, and a device responsive to the average square error of the clock signals varies the loop parameters of the loop filter means to minimize average square phase error.

Abstract: A system and method are disclosed for synchronizning the linear PN sequences contained in a received spread spectrum signal, characterized by the provision of a resident PN generator that is responsive to the chip rate clock for producing a replica of the PN sequence with arbitrary phase, a running matrix inverse of the matrix (R) formed by n successive observations of the register of the resident generator, and a matrix vector product device for multiplying the running inverse by a column vector of noisy chips, thereby to obtain a plurality of estimates of the phase vector. These estimates are smoothed and averaged to produce the smoothed phase vector (c.sub.j) that is applied to one input of a dot product device that operates in conjunction with the contents of the shift register of the resident generator to produce the properly phased PN sequence, which sequence is then supplied to despreading means for combining the noisy chips with the properly phased PN sequence.

Abstract: A method of transmitting binary data from one station to another via a troposcatter medium, characterized in that the data is converted to parallel form so that the bits produce distinctive pairs of sine and cosine harmonics having different frequencies, which harmonics are summed in two separated channels that are modulated by rf sine and cosine modulating signals that are combined and transmitted to the receiver, together with a test signal that was periodically inserted in the parallel bits. The receiver supplies the signals to banks of matched filters that produce a first set of signal estimates from which the test signal is detected. A matrix system responsive to the test signal produces from the first set of estimates a second set of signal estimates having lower distortion than the first set.

Abstract: A real time graphic processor is disclosed which processes graphic cell specifications on a scan line-by-line basis to generate pixel data. The pixel data from each cell specification is assembled to form a completed scan line of pixel data which is used to modulate a printing element, such as a laser diode. The invented graphic processor contains a special purpose cell specification processor which, in addition to generating the pixel data, modifies the cell specification by substituting new horizontal location and cell height indicator values. The modified graphic cell specification is then recirculated to the cell specification processor memory for processing the next scan line.

Abstract: Disclosed is a processor and method for the real time generation of linear arrays of pixel data. The generated pixel data is used to modulate a laser diode as it scans across a printing medium, thereby producing printed font and logo characters.In accordance with the present invention, the real time processor receives a series of cell specifications on a scan line-by-scan line basis, the cell specifications identifying the font type and placement information. The real-time processor uses this information to access from its font memory a linear array of pixel data corresponding to the identified font type. The accessed pixel data is used to modulate the laser diode as it scans the printing medium line-by-line. Thus, as the laser diode is modulated by the pixel's "ones" and "zeros", it is pulsed "off" and "on", thereby generating pixel dots on the print medium itself or on a photosensitive drum which subsequently prints an image on a page through an electrostatic process.

Abstract: A toner concentration sensor senses the concentration of toner in the toner system of an electro-photographic printer or copier. A novel circuit improves the toner concentration sensor. The novel circuit is composed of a resonant circuit, a frequency source, and a logic circuit. The resonant circuit is tuned to a selected frequency and has an inductor which creates a field into which the toner system is introduced. A frequency source excites the resonant circuit. A logic circuit receives a signal from the frequency source and an output from the resonant circuit. The logic circuit output is a signal representative of the phase shift between the signal from the frequency source and the output of the resonant circuit. The phase shift is representative of the inductance of the inductor in the presence of said toner system. The measurement of the inductance is representative of the concentration of toner in said toner system.

Abstract: A speed control circuit for a motor having a drive shaft which carries an optical encoder which generates pulses whose frequency is representative of the speed of the motor. The circuit includes a clock and a counter which generate a count between pulses, and a digital-to-analog converter (DAC) designed to receive each such count and to generate therefrom a corrective signal for maintaining the proper speed of the motor.