Abstract: A system may comprise a finite impulse response circuit configured to receive one or more samples of a first signal and generate an equalized signal based on the plurality of samples of the input signal and one or more updatable tap coefficients. The system may include an adaptation circuit configured to update the one or more updatable tap coefficients based on the plurality of samples of the input signal. The system may further comprise a recovery circuit configured to accumulate one or more retuning values based on the plurality of samples of the input signal and, in response to an error condition, generate one or more retuned tap coefficients for the finite impulse response circuit based on the one or more retuning values and replace the one or more updatable parameters with the one or more retuned parameters.

Abstract: A phase-locked loop (PLL) filter of a read channel includes a filter portion having an input coupled to delay circuitry having an output. The input of the filter portion is configured to receive a phase error signal. A look-up table is coupled to the filter portion. The look-up table comprises phase coefficients and frequency coefficients associated with a plurality of phase error magnitudes. The look-up table is configured to provide one or both of a selected phase coefficient and a selected frequency coefficient based on a magnitude of the phase error signal. The PLL filter is configured to adjust a bandwidth of the filter portion using one or both of the selected phase coefficient and the selected frequency coefficient. A phase signal indicative of estimated phase disturbance is produced at the output of the delay circuitry.

Abstract: In certain embodiments, an apparatus may comprise a circuit configured to receive a plurality of samples of an input signal. The circuit may update one or more equalizer parameters using partial zero forcing equalization. Further, the circuit may generate an equalized signal based on the plurality of samples of the input signal and the one or more equalizer parameters.

Abstract: A system may include an interpolator circuit configured to receive a first signal with a first rate and to generate an interpolated signal with a second rate. The system may include a cancellation circuit configured to determine an interference component signal based on the interpolated signal. The system may further comprise an adder configured to receive a second signal with the second rate and to cancel interference in the second signal using the interference component signal to generate a cleaned signal.

Abstract: A phase-locked loop (PLL) filter of a read channel includes a filter portion having an input coupled to delay circuitry having an output. The input of the filter portion is configured to receive a phase error signal. A look-up table is coupled to the filter portion. The look-up table comprises phase coefficients and frequency coefficients associated with a plurality of phase error magnitudes. The look-up table is configured to provide one or both of a selected phase coefficient and a selected frequency coefficient based on a magnitude of the phase error signal. The PLL filter is configured to adjust a bandwidth of the filter portion using one or both of the selected phase coefficient and the selected frequency coefficient. A phase signal indicative of estimated phase disturbance is produced at the output of the delay circuitry.

Abstract: A digitized signal is processed via an interpolator. The interpolator performs timing adjustment on the digitized signal. The error signal is determined based on a desired signal and the time-adjusted digitized signal. A corrective phase shift of the digitized signal is determined via a least-mean-squared processing block that uses the error and the derivative of a function used by the interpolator. The corrective phase shift is input to the interpolator to perform the timing adjustment.

Abstract: A phase-locked loop (PLL) filter of a read channel includes a filter portion having an input coupled to delay circuitry having an output. The input of the filter portion is configured to receive a phase error signal. A look-up table is coupled to the filter portion. The look-up table comprises phase coefficients and frequency coefficients associated with a plurality of phase error magnitudes. The look-up table is configured to provide one or both of a selected phase coefficient and a selected frequency coefficient based on a magnitude of the phase error signal. The PLL filter is configured to adjust a bandwidth of the filter portion using one or both of the selected phase coefficient and the selected frequency coefficient. A phase signal indicative of estimated phase disturbance is produced at the output of the delay circuitry.

Abstract: A digitized signal is processed via an interpolator. The interpolator performs timing adjustment on the digitized signal. The error signal is determined based on a desired signal and the time-adjusted digitized signal. A corrective phase shift of the digitized signal is determined via a least-mean-squared processing block that uses the error and the derivative of a function used by the interpolator. The corrective phase shift is input to the interpolator to perform the timing adjustment.

Abstract: Multiple input single output (MISO) systems and processes are presented that can adaptively equalize multiple signals to produce an output. In some examples, the MISO systems can include a fast transversal recursive least square (RLS) algorithm to produce the output. Fast transversal RLS algorithms can be less complex than other RLS algorithms. In some examples, the fast transversal RLS algorithm may be optimized to have no division operations. The MISO system may have two or more inputs.

Abstract: Method and apparatus for decoding data, such as from a rotatable magnetic recording medium. In accordance with some embodiments, a plurality of sensors is provided, with each sensor configured to generate a sense signal from an adjacent pattern. A processing circuit is configured to decode data from the adjacent pattern using the generated sense signals.

Abstract: Detecting track information involves receiving first and second overlapping track signals from first and second read elements that read first and second tracks from a data storage medium. Information of the first and second tracks is estimated using the respective first and second track signals. An improved information estimate of the first track is obtained using the first track signal and the estimated information of the second track, and an improved information estimate of the second track is obtained using the second track signal and the estimated information of the first track. First and second track data are decoded using the respective improved information estimates of the first and second tracks.

Abstract: A system can include a first buffer storing a first fragment of data for a first data sector in a first track of a storage medium, a second buffer storing a second fragment of data for a second data sector in a second track of the storage medium adjacent to the first track, a processor configured to determine an estimated region of overlap between the first data fragment and the second data fragment, and a circuit configured to refine the estimated region of overlap by determining an offset value to offset an estimated beginning portion of overlap by the second fragment.

Abstract: Method and apparatus for decoding data, such as from a rotatable magnetic recording medium. In accordance with some embodiments, a plurality of sensors is provided, with each sensor configured to generate a sense signal from an adjacent pattern. A processing circuit is configured to decode data from the adjacent pattern using the generated sense signals.

Abstract: Detecting track information involves receiving first and second overlapping track signals from first and second read elements that read first and second tracks from a data storage medium. Information of the first and second tracks is estimated using the respective first and second track signals. An improved information estimate of the first track is obtained using the first track signal and the estimated information of the second track, and an improved information estimate of the second track is obtained using the second track signal and the estimated information of the first track. First and second track data are decoded using the respective improved information estimates of the first and second tracks.

Abstract: An equalizer configured to receive a data signal from a channel. The detector is coupled to the equalizer, and a calibration unit is coupled with the equalizer and the detector. The calibration unit is configured to jointly calibrate the equalizer and the detector using a metric subject to an entropy-preserving equalizer constraint.

Abstract: An equalizer configured to receive a data signal from a channel. The detector is coupled to the equalizer, and a calibration unit is coupled with the equalizer and the detector. The calibration unit is configured to jointly calibrate the equalizer and the detector using a metric subject to an entropy-preserving equalizer constraint.

Abstract: Devices, methods, and systems of a communications channel detector are disclosed that can compare a plurality of candidate sequences of bits and decisions to identify unlikely error events. The detector may then discard at least one candidate sequence based on an unlikely error event to produce a set of remaining paths. A branch metric calculator may be adapted to calculate metrics for a set of remaining paths.

Abstract: An approach to reducing processing of soft output is disclosed. Candidate sequences of bits can be compared to soft output decisions to reduce at least one of the candidate sequences. Branch metric calculations can be performed for remaining candidate sequences and a most likely path can be selected from the remaining candidate sequences.

Abstract: A communications channel is provided that includes an encoder that receives user data and generates corresponding encoded symbols for transmission through a channel medium. A channel detector has an input coupled to receive an output signal from the channel medium and a reliability information output which produces reliability information regarding logic states of detected bits in the output signal. A binary reliability value is provide for each of the detected bits. The channel further includes a decoder having a reliability information input coupled to the reliability information output of the channel detector to generate corresponding user data words as a function of the binary reliability value.