Patents by Inventor William R. Bryg

William R. Bryg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7103728
    Abstract: A distributed-memory multi-processor system includes a plurality of cells communicatively coupled to each other and collectively including a plurality of processors, caches, main memories, and cell controllers. Each of the cells includes at least one of the processors, at least one of the caches, one of the main memories, and one of the cell controllers. Each of the cells is configured to perform memory migration functions for migrating memory from a first one of the main memories to a second one of the main memories in a manner that is invisible to an operating system of the system.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: September 5, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Debendra Das Sharma, Ashish Gupta, William R. Bryg
  • Patent number: 6874070
    Abstract: A method of accessing a plurality of memories in an interleaved manner using a contiguous logical address space includes providing at least one map table. The at least one map table includes a plurality of entries. Each entry includes a plurality of entry items. Each entry item identifies one of the memories. A first logical address is received. The first logical address includes a plurality of address bits. The plurality of address bits includes a first set of address bits corresponding to a first set of entries in the at least one map table. A first entry in the first set of entries is identified based on the first set and a second set of the address bits. A first entry item in the first entry is identified based on a third set of the address bits. The memory identified by the first entry item is accessed.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: March 29, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ashish Gupta, William R. Bryg
  • Patent number: 6820086
    Abstract: A linked list structure in a computing system includes a first entry and additional entries. Each additional entry includes a link reference to a prior entry in the linked list. The link reference for each additional entry all are stored within a content addressable memory. Each additional entry is accessible by performing a content search using the link reference to the prior entry. The linked list is traversed by accessing the first entry in the linked list. A second entry in the linked list is accessed by searching the content addressable memory with an index of the first entry. A third entry in the linked list is accessed by searching the content addressable memory with an index of the second entry.
    Type: Grant
    Filed: June 18, 1999
    Date of Patent: November 16, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Sorin Iacobovici, William R. Bryg, Joseph H. Hassoun
  • Publication number: 20040019751
    Abstract: A distributed-memory multi-processor system includes a plurality of cells communicatively coupled to each other and collectively including a plurality of processors, caches, main memories, and cell controllers. Each of the cells includes at least one of the processors, at least one of the caches, one of the main memories, and one of the cell controllers. Each of the cells is configured to perform memory migration functions for migrating memory from a first one of the main memories to a second one of the main memories in a manner that is invisible to an operating system of the system.
    Type: Application
    Filed: July 23, 2002
    Publication date: January 29, 2004
    Inventors: Debendra Das Sharma, Ashish Gupta, William R. Bryg
  • Publication number: 20030167383
    Abstract: A method of accessing a plurality of memories in an interleaved manner using a contiguous logical address space includes providing at least one map table. The at least one map table includes a plurality of entries. Each entry includes a plurality of entry items. Each entry item identifies one of the memories. A first logical address is received. The first logical address includes a plurality of address bits. The plurality of address bits includes a first set of address bits corresponding to a first set of entries in the at least one map table. A first entry in the first set of entries is identified based on the first set and a second set of the address bits. A first entry item in the first entry is identified based on a third set of the address bits. The memory identified by the first entry item is accessed.
    Type: Application
    Filed: February 22, 2002
    Publication date: September 4, 2003
    Inventors: Ashish Gupta, William R. Bryg
  • Patent number: 6430670
    Abstract: The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of the Translation Lookaside Buffer (TLB) hierarchy, is designed to enhance virtual address translation performance. Virtual Hash Page Table (VHPT) efficiently supports two different methods of operating systems use to translate virtual addresses to physical addresses. This directly benefits the highly frequented path of address resolution.
    Type: Grant
    Filed: November 1, 2000
    Date of Patent: August 6, 2002
    Assignee: Hewlett-Packard Co.
    Inventors: William R. Bryg, Stephen G. Burger, James O. Hays, John M. Kessenich, Jonathan K. Ross, Gary N. Hammond, Sunil Saxena, Koichi Yamada
  • Patent number: 6408373
    Abstract: A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can be bypassed when performing most TLB accesses, thereby removing region registers the critical path of the TLB look-up process and enhancing system performance. A TLB in accordance with the present invention includes entries having a valid field, a region pre-validation valid (rpV) field, a virtual region number (VRN) field, a virtual page number (VPN) field, a region identifier (RID) field, a protection and access attributes field, and a physical page number (PPN) field. In addition, a set of region registers contains the RIDs that are active at any given time.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: June 18, 2002
    Assignee: Institute for the Development of Emerging Architectures, LLC
    Inventors: Stephen G. Burger, James O. Hays, Jonathan K. Ross, William R. Bryg, Rajiv Gupta, Gary N. Hammond, Koichi Yamada
  • Patent number: 6393544
    Abstract: A method and apparatus calculate a page table index from a virtual address. Employs a combined hash algorithm that supports two different hash page table configurations. A “short format” page table is provided for each virtual region, is linear, has a linear entry for each translation in the region, and does not store tags or chain links. A single “long format” page table is provided for the entire system, supports chained segments, and includes hash tag fields. The method of the present invention forms an entry address from a virtual address, with the entry address referencing an entry of the page table. To form the entry address, first a hash page number is formed from the virtual address by shifting the virtual address right based on the page size of the region of the virtual address.
    Type: Grant
    Filed: October 31, 1999
    Date of Patent: May 21, 2002
    Assignee: Institute for the Development of Emerging Architectures, L.L.C.
    Inventors: William R. Bryg, Stephen G. Burger, Gary N. Hammond, James O. Hays, Jerome C. Huck, Jonathan K. Ross, Sunil Saxena, Koichi Yamada
  • Patent number: 6304932
    Abstract: A shared bus system having a bus and a set of client modules coupled to the bus. Each client module is capable of sending transactions on the bus to other client modules and receiving transactions on the bus from other client modules for processing. Each module has a queue for storing transactions received by the module for processing. A bus controller limits the types of transactions that can be sent on the bus to prevent any module's queue from overflowing.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: October 16, 2001
    Assignee: Hewlett-Packard Company
    Inventors: Michael L. Ziegler, Robert J. Brooks, William R. Bryg, Craig R. Frink, Thomas R. Hotchkiss, Robert D. Odineal, James B. Williams, John L. Wood
  • Publication number: 20010021969
    Abstract: A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can be bypassed when performing most TLB accesses, thereby removing region registers the critical path of the TLB look-up process and enhancing system performance. A TLB in accordance with the present invention includes entries having a valid field, a region pre-validation valid (rpV) field, a virtual region number (VRN) field, a virtual page number (VPN) field, a region identifier (RID) field, a protection and access attributes field, and a physical page number (PPN) field. In addition, a set of region registers contains the RIDs that are active at any given time.
    Type: Application
    Filed: May 7, 2001
    Publication date: September 13, 2001
    Inventors: Stephen G. Burger, James O. Hays, Jonathan K. Ross, William R. Bryg, Rajiv Gupta, Gary N. Hammond, Koichi Yamada
  • Patent number: 6230248
    Abstract: A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can be bypassed when performing most TLB accesses, thereby removing region registers the critical path of the TLB look-up process and enhancing system performance. A TLB in accordance with the present invention includes entries having a valid field, a region pre-validation valid (rpV) field, a virtual region number (VRN) field, a virtual page number (VPN) field, a region identifier (RID) field, a protection and access attributes field, and a physical page number (PPN) field. In addition, a set of region registers contains the RIDs that are active at any given time.
    Type: Grant
    Filed: October 12, 1998
    Date of Patent: May 8, 2001
    Assignee: Institute for the Development of Emerging Architectures, L.L.C.
    Inventors: Stephen G. Burger, James O. Hays, Jonathan K. Ross, William R. Bryg, Rajiv Gupta, Gary N. Hammon, Koichi Yamada
  • Patent number: 6216214
    Abstract: The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of the Translation Lookaside Buffer (TLB) hierarchy, is designed to enhance virtual address translation performance. Virtual Hash Page Table (VHPT) efficiently supports two different methods of operating systems use to translate virtual addresses to physical addresses. This directly benefits the highly frequented path of address resolution.
    Type: Grant
    Filed: February 3, 1998
    Date of Patent: April 10, 2001
    Assignee: Institute for the Development of Emerging Architectures, L.L.C.
    Inventors: William R. Bryg, Stephen G. Burger, James O. Hays, John M. Kessenich, Jonathan K. Ross, Gary N. Hammond, Sunil Saxena, Koichi Yamada
  • Patent number: 6199144
    Abstract: A method and apparatus for transferring data from a first memory location to a second memory location in a computer system. A load instruction is executed, and, in response, data is transferred from a first memory location to a second memory location during a single bus transaction. During the same bus transaction, a request is made to invalidate a copy of the data that is stored in a third memory location if the load instruction indicates to do so.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: March 6, 2001
    Assignee: Intel Corporation
    Inventors: Judge K. Arora, William R. Bryg, Stephen G. Burger, Gary N. Hammond, Michael L. Ziegler
  • Patent number: 6182176
    Abstract: A shared bus system having a bus and a set of client modules coupled to the bus. Each client module is capable of sending transactions on the bus to other client modules and receiving transactions on the bus from other client modules for processing. Each module has a queue for storing transactions received by the module for processing. A bus controller limits the types of transactions that can be sent on the bus to prevent any module's queue from overflowing.
    Type: Grant
    Filed: February 24, 1994
    Date of Patent: January 30, 2001
    Assignee: Hewlett-Packard Company
    Inventors: Michael L. Ziegler, Robert J. Brooks, William R. Bryg, Craig R. Frink, Thomas R. Hotchkiss, Robert D. Odineal, James B. Williams, John L. Wood
  • Patent number: 6128706
    Abstract: Apparatus and method for efficiently sharing data in support of hardware he coherency and coordinated in software with semaphore instructions. Accordingly, a new instruction called "Load-Bias" which, in addition to normal load operations, requests a private copy of the data, and hints to the hardware cache to try to maintain ownership until the next memory reference from that processor. When used with the Cmpxchg instruction semaphore operation, the Load-Bias instruction will reduce coherency traffic, and minimize the possibility of coherency ping-ponging or system deadlock that causes the condition in which no processor is getting useful work done.
    Type: Grant
    Filed: February 3, 1998
    Date of Patent: October 3, 2000
    Assignee: Institute for the Development of Emerging Architectures, L.L.C.
    Inventors: William R. Bryg, Stephen G. Burger, Gary N. Hammond, Michael L. Ziegler
  • Patent number: 6108721
    Abstract: In a method and apparatus that ensures data consistency between an I/O channel and a processor, system software issues an instruction which causes the issuance of a transaction when notification of a DMA completion is received. The transaction instructs the I/O channel to enforce coherency and then responds back only after coherency has been ensured. Specifically, a DMA.sub.-- SYNC transaction is broadcast to all I/O channels in the system. Responsive thereto, each I/O channel writes back to memory any modified lines in its cache that might contain DMA data for a DMA sequence that was reported by the system as completed. The I/O channels have a reporting means to indicate when this transaction is completed, so that the DMA.sub.-- SYNC transaction does not have to complete in pipeline order. Thus, the I/O channel can issue new transactions before responding to the DMA.sub.-- SYNC transaction.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: August 22, 2000
    Assignee: Hewlett-Packard Company
    Inventors: William R. Bryg, Monish S. Shah, Thomas V. Spencer
  • Patent number: 6088780
    Abstract: A method and apparatus for implementing a page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address. According to one aspect of the invention, an apparatus for use in a computer system is provided that includes a page size storage area and a page table walker. The page size storage area is used to store a number of page sizes each selected for translating a different set of virtual addresses. The page table walker includes a selection unit coupled to the page size storage area, as well as a page entry address generator coupled to the selection unit. For each of the virtual address received, the selection unit positions a field in that virtual address based on the page size selected for translating the set of virtual addresses to which that virtual address belongs.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: July 11, 2000
    Assignee: Institute for the Development of Emerging Architecture, L.L.C.
    Inventors: Koichi Yamada, Gary N. Hammond, Jim Hays, Jonathan Kent Ross, Stephen Burger, William R. Bryg
  • Patent number: 6079012
    Abstract: A computer apparatus which detects a store or load operation into or from a shared memory page by a program that does not provide for synchronization when executed by a CPU that completes instructions out of program order. After the store or load is detected, the CPU explicitly orders operations into the shared memory page. Store operations are ordered such that no new store into the shared memory page is performed until all prior store operations into the shared memory page are complete. Also, load operations are ordered such that load operations from the shared memory page are performed in program order. This ordering is achieved by maintaining a process bit and a memory attribute bit associated with a shared memory page. When both bits are true, all load or store operations referencing the shared memory page are ordered.
    Type: Grant
    Filed: November 6, 1997
    Date of Patent: June 20, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Dale C. Morris, Bernard L. Stumpf, Barry J. Flahive, Jeffrey D. Kurtze, Stephen G. Burger, Ruby B. L. Lee, William R. Bryg
  • Patent number: 6049851
    Abstract: A double cache snoop mechanism in uniprocessor computer systems having a cache and coherent I/O and multiprocessor computer systems reduces the number of cycles that a processor is stalled during a coherency check. The snoop mechanism splits each coherency check, such that a read-only check is first sent to the cache subsystem., and a read-write check is sent thereafter only if there is a cache hit during the read-only check, and there is the need to modify the cache. Average processor pipeline stall time is reduced even though a cache hit results in an additional coherency check because most coherency checks do not result in a cache hit.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: April 11, 2000
    Assignee: Hewlett-Packard Company
    Inventors: William R. Bryg, Kenneth K. Chan, Eric Delano, John F. Shelton
  • Patent number: 6006325
    Abstract: A new instruction that ensures that the effects of a control register write will be observed at a well defined time is introduced. Specifically, the present invention introduces the concept of a serialization fence instruction. The serialization fence instruction ensures that after a control register in a computer has been modified, all subsequent instructions will observe the effects of the control register modification. Two different serialization fence instructions are illustrated: a data memory reference serialization fence instruction (SRLZ.d) and an instruction fetch serialization fence instruction (SRLZ.i). The data memory reference serialization fence instruction ensures that subsequent instruction executions and data memory references will observe the effects of the control register write. The instruction fetch serialization fence instruction ensures that the entire machine pipeline, starting at the initial instruction fetch stage, will observe the effects of the control register write.
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: December 21, 1999
    Assignee: Institute for the Development of Emerging Architectures, L.L.C.
    Inventors: Stephen Burger, Gary N. Hammond, William R. Bryg