Abstract: A multilayer passive circuit topology is disclosed. In one embodiment, a multilayer circuit is provided. The multilayer circuit comprises a multilayer inductor comprising a first set of parallel conductive traces formed on a first layer, a second set of parallel conductive traces formed on a second layer spaced apart from the first layer; and a plurality of vias that connect respective parallel conductive traces from the first and second layer to form inductor windings. The multilayer circuit further comprises a multilayer capacitor connected to an end of the inductor by a coupling via, the capacitor comprising a first conductive plate and a second conductive plate being spaced apart from one another and being formed on different layers.

Abstract: A multilayer passive circuit topology is disclosed. In one embodiment, a multilayer circuit is provided. The multilayer circuit comprises a multilayer inductor comprising a first set of parallel conductive traces formed on a first layer, a second set of parallel conductive traces formed on a second layer spaced apart from the first layer; and a plurality of vias that connect respective parallel conductive traces from the first and second layer to form inductor windings. The multilayer circuit further comprises a multilayer capacitor connected to an end of the inductor by a coupling via, the capacitor comprising a first conductive plate and a second conductive plate being spaced apart from one another and being formed on different layers.

Abstract: An integrated circuit (IC) resonator in which resonator parameters potentially affected by IC fabrication processes are correctable after fabrication. Resonance frequency tuning is effected by forming each feedback capacitor in a pair of integrator circuits to include a variable capacitance device, such as a varactor diode. A tuning signal is applied to the varactor diode to adjust the total capacitance value and, therefore, the resonance frequency. Similarly, the quality (Q) factor of the resonator is adjusted by providing a variable capacitance in an RC (resistance-capacitance) network coupling the output of one of the integrator circuits to the input of the other. The variable capacitance in the RC network permits adjustment of phase in the event that the integrator circuits do not provide a desired 180° total phase shift.

Abstract: A loop-back self-test circuit (10) that has particular application for a cellular telephone base station, where the components of the self-test circuit (10) are integrated on a common integrated circuit chip (20). The transmit signal and an LO signal are applied to a mixer (28) to convert the frequency of the transmit signal to the frequency of a receive signal. A VCO (56) generates the LO signal and a PLL (26) synchronizes the phase of the VCO signal to the phase of a reference signal. A divided reference signal and a divided VCO signal are applied to a phase comparator (52) that generates an error signal indicative of the phase difference between the reference signal and the VCO signal. The error signal is applied to a charge pump (60) that generates a current signal to tune a tank circuit (66). A voltage signal from a loop filter (62) is applied to the VCO (56) to tune it to the LO frequency.

Abstract: A circuit for supplying selected currents to a charge pump without harmful effects arising from operation of current switches in the charge pump. A charge pump current setting is applied in digital form to a set of two-position switches coupled to binary-weighted current sources. Currents from the sources selected by the switches are combined, and the total current is mirrored to the charge pump. Simultaneously, those of the binary-weighted current sources not selected by the switches to contribute to the charge pump current are separately combined, and this total current is mirrored to an electrical replica of the charge pump. Thus the currents supplied to the charge pump and to the replica charge pump are complementary in the sense that they always add to a constant total current drawn from a common power supply. Therefore, abrupt changes in current load are avoided and switching noise effects are minimized.

Abstract: A diversity receiver circuit system (10) including a primary channel (20) and a diversity channel (22), where analog input signals are converted to differential signals in both channels (20, 22). The receiver circuit system (10) includes a multiplexer (14) and a variable gain amplifier (12) formed on a single RF integrated circuit chip (16), where the multiplexer (14) is positioned before the amplifier (12). The differential signals in the primary channel (20) and the diversity channel (22) are applied to an amplified path (72, 78) and a non-amplified path (76, 82) in the multiplexer (14). A control signal selects one of the amplified primary channel signal, the non-amplified primary channel signal, the amplified diversity channel signal or the non-amplified diversity channel signal.

Abstract: An integrated switched filterbank and method of forming an integrated switched filterbank is disclosed. One embodiment includes a switched filterbank that includes an active subassembly, a plurality of active devices mounted to the active subassembly, and a stripline filter subassembly stacked below the active subassembly. The stripline filter subassembly includes a plurality of stripline filters of varying passbands embedded therein, wherein the plurality of stripline filters are coupled to active devices mounted on the active subassembly through a set of contacts extending from the stripline filters through the active subassembly to at least one of the plurality of active devices.

Abstract: A low noise amplifier (LNA) has a selectable bypass signal path integrated into the same integrated circuit (IC) as the amplifier components. In a normal mode of operation, an integrated mode switch allows an appropriate biasing signal to be applied LNA transistors, which function to amplify an input signal and produce an amplified output signal. In an attenuation mode, which is activated to handle large input signals, the LNA transistors are switched off and the input signal is attenuated by a voltage divider, which provides an attenuated output on a signal path that bypasses the LNA amplifier. An attenuation switching signal not only operates the mode switch in the LNA, but also selects between the normal and bypass outputs of the LNA, for further amplification downstream of the LNA.

Abstract: A low noise amplifier (LNA) has a selectable bypass signal path integrated into the same integrated circuit (IC) as the amplifier components. In a normal mode of operation, an integrated mode switch allows an appropriate biasing signal to be applied LNA transistors, which function to amplify an input signal and produce an amplified output signal. In an attenuation mode, which is activated to handle large input signals, the LNA transistors are switched off and the input signal is attenuated by a voltage divider, which provides an attenuated output on a signal path that bypasses the LNA amplifier. An attenuation switching signal not only operates the mode switch in the LNA, but also selects between the normal and bypass outputs of the LNA, for further amplification downstream of the LNA.

Abstract: A lumped element ring balun (60) including elements patterned on a monolithic substrate (62) in a compact design. The balun (60) includes four inductors (64, 66, 68, 70) and a plurality of capacitors (190, 192, 198, 202, 214, 226) electrically coupled together to provide RF output signals that are 180° out of phase with each other. The inductors (64-70) are symmetrically disposed in a rectangular area on the substrate (62). A first pair of the inductors (64, 66) is positioned at one end of the rectangular area, and a second pair of the inductors (68, 70) is positioned at opposite end of the rectangular area. All of the capacitors are formed on the substrate (62) in a central circuit area (72) between the first pair of inductors (64, 66) and the second pair of inductors (68, 70). Inner ends (76, 92, 98, 106) are coupled to circuit elements in the circuit area (72) by a metallized trace (120, 136, 150, 170) extending through an air bridge (124, 140, 154, 174).

Abstract: A differential PIN diode attenuator (450) that selectively attenuates a differential analog input signal. The two parts of the differential signal are applied to separate input lines (452, 454) and are 180° out of phase with each other. One input line (452) is coupled to a first attenuation path (456) including a resistor and a first non-attenuation path (458) including a PIN diode (462). The other input line (454) is coupled to a second attenuation path (466) including a resistor and a second non-attenuation path (468) including a PIN diode (472). The diodes (462, 472) are biased by a DC bias signal so that the differential analog signal can bypass the attenuation paths (456, 466). The DC bias signal is applied halfway between the input lines (452, 454) where the two parts of the differential signal cancel. A shunt diode (490, 492,) and parallel shunt resistors are provided in combination with the attenuation resistor to allow it to have a relatively small value.

Abstract: A circuit layout for a lumped element dual-balun (248) where the elements of the dual-balun (248) are patterned on a monolithic substrate (250) in a compact design. The dual-balun (248) includes four inductors (252, 254, 256, 258) and four capacitors (340, 342, 360, 388) electrically coupled together to provide two zero phase RF output signals and two 180° phase RF output signals. The inductors (252, 254, 256, 258) are symmetrically disposed in a rectangular area on the substrate (250). A first pair of the inductors (252, 254) is positioned at one end of the rectangular area, and a second pair of the inductors (256, 258) is positioned at an opposite end of the rectangular area. The capacitors (340, 342, 360, 388) are formed on the monolithic substrate (250) in a central circuit area (260) between the first pair (252, 254) and the second pair of inductors (256, 258).

Abstract: A method of routing a frequency hopping signal to one of two transmitting antennas in a multiple carrier communication system is disclosed. The method comprises storing known a-priori information regarding frequency hopping signal assignments, scanning a transmitter frequency and antenna path assignment table to determine the closest existing transmitting frequency and its antenna to the frequency hopping signal to be assigned, assigning the frequency hopping signal to an available path on the other antenna, and updating the transmitter frequency and antenna path assignment table. In addition the method includes determining whether the assigned path on the other antenna conflicts with existing frequency assignments, and preempting the antenna assignment when a conflict exists.

Abstract: A loop-back self-test circuit (10) that has particular application for a cellular telephone base station, where the components of the self-test circuit (10) are integrated on a common integrated circuit chip (20). The transmit signal and an LO signal are applied to a mixer (28) to convert the frequency of the transmit signal to the frequency of a receive signal. A VCO (56) generates the LO signal and a PLL (26) synchronizes the phase of the VCO signal to the phase of a reference signal. A divided reference signal and a divided VCO signal are applied to a phase comparator (52) that generates an error signal indicative of the phase difference between the reference signal and the VCO signal. The error signal is applied to a charge pump (60) that generates a current signal to tune a tank circuit (66). A voltage signal from a loop filter (62) is applied to the VCO (56) to tune it to the LO frequency.

Abstract: A circuit layout for a lumped element dual-balun (248) where the elements of the dual-balun (248) are patterned on a monolithic substrate (250) in a compact design. The dual-balun (248) includes four inductors (252, 254, 256, 258) and four capacitors (340, 342, 360, 388) electrically coupled together to provide two zero phase RF output signals and two 180° phase RF output signals. The inductors (252, 254, 256, 258) are symmetrically disposed in a rectangular area on the substrate (250). A first pair of the inductors (252, 254) is positioned at one end of the rectangular area, and a second pair of the inductors (256, 258) is positioned at an opposite end of the rectangular area. The capacitors (340, 342, 360, 388) are formed on the monolithic substrate (250) in a central circuit area (260) between the first pair (252, 254) and the second pair of inductors (256, 258).

Abstract: A lumped element ring balun (60) including elements patterned on a monolithic substrate (62) in a compact design. The balun (60) includes four inductors (64, 66, 68, 70) and a plurality of capacitors (190, 192, 198, 202, 214, 226) electrically coupled together to provide RF output signals that are 180° out of phase with each other. The inductors (64-70) are symmetrically disposed in a rectangular area on the substrate (62). A first pair of the inductors (64, 66) is positioned at one end of the rectangular area, and a second pair of the inductors (68, 70) is positioned at opposite end of the rectangular area. All of the capacitors are formed on the substrate (62) in a central circuit area (72) between the first pair of inductors (64, 66) and the second pair of inductors (68, 70). Inner ends (76, 92, 98, 106) are coupled to circuit elements in the circuit area (72) by a metallized trace (120, 136, 150, 170) extending through an air bridge (124, 140, 154, 174).

Abstract: A differential PIN diode attenuator (450) that selectively attenuates a differential analog input signal. The two parts of the differential signal are applied to separate input lines (452, 454) and are 180° out of phase with each other. One input line (452) is coupled to a first attenuation path (456) including a resistor and a first non-attenuation path (458) including a PIN diode (462). The other input line (454) is coupled to a second attenuation path (466) including a resistor and a second non-attenuation path (468) including a PIN diode (472). The diodes (462, 472) are biased by a DC bias signal so that the differential analog signal can bypass the attenuation paths (456, 466). The DC bias signal is applied halfway between the input lines (452, 454) where the two parts of the differential signal cancel. A shunt diode (490, 492,) and parallel shunt resistors are provided in combination with the attenuation resistor to allow it to have a relatively small value.

Abstract: A diversity receiver circuit system (10) including a primary channel (20) and a diversity channel (22), where analog input signals are converted to differential signals in both channels (20, 22). The receiver circuit system (10) includes a multiplexer (14) and a variable gain amplifier (12) formed on a single RF integrated circuit chip (16), where the multiplexer (14) is positioned before the amplifier (12). The differential signals in the primary channel (20) and the diversity channel (22) are applied to an amplified path (72, 78) and a non-amplified path (76, 82) in the multiplexer (14). A control signal selects one of the amplified primary channel signal, the non-amplified primary channel signal, the amplified diversity channel signal or the non-amplified diversity channel signal.

Abstract: An impedance matched frequency dependent gain compensation network for multi-octave passband equalization. A first stage amplifier outputs an amplified signal to an equalizer, which in turn outputs an equalized signal to a second stage amplifier. The equalizer varies the attenuation in accordance with the frequency to provide minimum gain variation, thereby providing optimal noise characteristics and generally constant linearity.