Patents by Inventor William R. Kelly

William R. Kelly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190350616
    Abstract: An apparatus includes a shaft assembly, an ultrasonic blade, and a clamp assembly. The shaft assembly includes an acoustic waveguide operable to transmit ultrasonic vibrations to the blade. The clamp assembly includes a clamp arm pivotable toward and away from the blade about a pivot axis, to clamp tissue between the clamp arm and the blade. A rotation feature may provide rotation of the blade relative to the clamp arm about the longitudinal axis of the waveguide. Alternatively, the rotation feature may provide rotation of the clamp arm relative to the blade about the longitudinal axis. The rotation feature may be driven based on pivotal positioning of the clamp arm relative to the blade about the pivot axis. The rotation feature may selectively lock and unlock the angular position of either the blade or the clamp arm about the longitudinal axis at any of a number of predetermined angular positions.
    Type: Application
    Filed: June 3, 2019
    Publication date: November 21, 2019
    Inventors: Craig N. Faller, Elizabeth DeBenedictis, William D. Kelly, Michael R. Lamping, Timothy G. Dietz, Patrick A. Weizman, Jacob S. Gee, John B. Schulte, Tylor C. Muhlenkamp, Douglas J. Turner, Eric B. Smith, Sean P. Conlon, Richard W. Timm, Jeffrey D. Messerly, Brian D. Bertke
  • Patent number: 10470792
    Abstract: An apparatus includes a shaft assembly, an ultrasonic blade, and a clamp assembly. The shaft assembly includes an acoustic waveguide operable to transmit ultrasonic vibrations to the blade. The clamp assembly includes a clamp arm pivotable toward and away from the blade about a pivot axis, to clamp tissue between the clamp arm and the blade. A rotation feature may provide rotation of the blade relative to the clamp arm about the longitudinal axis of the waveguide. Alternatively, the rotation feature may provide rotation of the clamp arm relative to the blade about the longitudinal axis. The rotation feature may be driven based on pivotal positioning of the clamp arm relative to the blade about the pivot axis. The rotation feature may selectively lock and unlock the angular position of either the blade or the clamp arm about the longitudinal axis at any of a number of predetermined angular positions.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: November 12, 2019
    Assignee: Ethicon LLC
    Inventors: Craig N. Faller, Elizabeth DeBenedictis, William D. Kelly, Michael R. Lamping, Timothy G. Dietz, Patrick A. Weizman, Jacob S. Gee, John B. Schulte, Tylor C. Muhlenkamp, Douglas J. Turner, Eric B. Smith, Sean P. Conlon, Richard W. Timm, Jeffrey D. Messerly, Brian D. Bertke
  • Publication number: 20190325654
    Abstract: A system, device, and method for a real-time 3D augmented reality common operating picture (COP) enables at least one user to see all players in the environment using real-time data to populate movement and characteristics and interact with the environment to collaboratively see relevant information needed for their mission and purpose. Components include data processing system(s) 805; processor(s) 810; program code 815; computer readable storage medium 820; 3D display(s) 825; 3D environment model(s) 830; security module 835; time source 840; external source data 845; air platform(s) 850; land platform(s) 855; sea platform(s) 860; and user input 865. Operation involve environment identification 905; 3D model selection 1010; memory pool population 1015; 3D environment generation 1020; 3D environment display 1025; external data source selection 1030; external data source input 1035; platform display in 3D environment 1040; user input 1045; data panel display 1050; and system update 1055.
    Type: Application
    Filed: April 24, 2018
    Publication date: October 24, 2019
    Inventors: Karissa M. Stisser, Christopher R. Cummings, John J. Kelly, Fran A. Piascik, William R. Samuels, Michelle R. Wingert
  • Patent number: 10391228
    Abstract: A hemodialysis system configured to purge air from a blood circuit comprises a dialyzer; a dialysis fluid circuit operable with the dialyzer via dialysis fluid inlet and outlet lines, the dialysis fluid circuit including a fresh dialysis fluid pump, and a used dialysis fluid pump; the blood circuit operable with the dialyzer and including an arterial line, a venous line, a blood pump operable with the arterial line upstream of the dialyzer, a physiologically acceptable fluid source in fluid communication with the arterial line upstream of the blood pump, a drip chamber located along the venous line, and a container for accepting air purged from the blood circuit; and an air purging scheme wherein, with the dialysis fluid inlet and outlet lines connected to the dialyzer, the blood pump pumps a fluid through the dialyzer and into the drip chamber, forcing air from the drip chamber into the container.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: August 27, 2019
    Assignees: BAXTER INTERNATIONAL INC., BAXTER HEALTHCARE SA
    Inventors: Thomas D. Kelly, Marc S. Minkus, Angelito A. Bernardo, William P. Burns, Robert W. Childers, Shincy J. Maliekkal, Matthew R. Muller, Justin B. Rohde, Michael E. Hogard
  • Publication number: 20190167887
    Abstract: A hemodialysis system configured to purge air from a blood circuit comprises a dialyzer; a dialysis fluid circuit operable with the dialyzer via dialysis fluid inlet and outlet lines, the dialysis fluid circuit including a fresh dialysis fluid pump, and a used dialysis fluid pump; the blood circuit operable with the dialyzer and including an arterial line, a venous line, a blood pump operable with the arterial line upstream of the dialyzer, a physiologically acceptable fluid source in fluid communication with the arterial line upstream of the blood pump, a drip chamber located along the venous line, and a container for accepting air purged from the blood circuit; and an air purging scheme wherein, with the dialysis fluid inlet and outlet lines connected to the dialyzer, the blood pump pumps a fluid through the dialyzer and into the drip chamber, forcing air from the drip chamber into the container.
    Type: Application
    Filed: February 8, 2019
    Publication date: June 6, 2019
    Inventors: Thomas D. Kelly, Marc S. Minkus, Angelito A. Bernardo, William P. Burns, Robert W. Childers, Shincy J. Maliekkal, Matthew R. Muller, Justin B. Rohde, Michael E. Hogard
  • Patent number: 9235543
    Abstract: A system for detecting one or more signals at a PCI Express interface includes a receiver configured to receive a signal at the PCI Express interface, and a peak detector configured to detect one or more signals based on level sensing, and identify one or more data sampling points to set an amplitude threshold. A comparator is configured to compare an amplitude of the received signal with the amplitude threshold, and a processor is configured to confirm that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The processor is also configured to disable a signal detector that can detect one or more low frequency signals. The system also includes a tester configured to test whether the detected signal is correct.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: January 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Hayden C Cranford, Jr., Daniel M Dreps, William R Kelly
  • Patent number: 9213667
    Abstract: Methods for detecting one or more signals at a PCI Express interface includes receiving, a signal by a receiver at the PCI Express interface. The methods further include identifying one or more data sampling points to set an amplitude threshold. Further, the method includes comparing an amplitude of the received signal with the amplitude threshold. The method also includes confirming that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The method also includes disabling a signal detector of the PCI Express interface to save power. The signal detector is configured to detect one or more low frequency signals; and testing whether the detected signal is correct.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: December 15, 2015
    Assignee: International Business Machines Corporation
    Inventors: Hayden C Cranford, Jr., Daniel M Dreps, William R Kelly
  • Patent number: 9209948
    Abstract: Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: December 8, 2015
    Assignee: International Business Machines Corporation
    Inventors: Eugene R. Atwood, Matthew B. Baecher, Minhan Chen, Hayden C. Cranford, Jr., William R. Kelly, Todd M. Rasmus
  • Publication number: 20150145710
    Abstract: Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: International Business Machines Corporation
    Inventors: EUGENE R. ATWOOD, MATTHEW B. BAECHER, WILLIAM R. KELLY, JOSEPH F. LOGAN, PINPING SUN
  • Patent number: 9041572
    Abstract: Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Eugene R. Atwood, Matthew B. Baecher, William R. Kelly, Joseph F. Logan, Pinping Sun
  • Publication number: 20150131707
    Abstract: Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.
    Type: Application
    Filed: January 19, 2015
    Publication date: May 14, 2015
    Inventors: EUGENE R. ATWOOD, MATTHEW B. BAECHER, MINHAN CHEN, HAYDEN C. CRANFORD, JR., WILLIAM R. KELLY, TODD M. RASMUS
  • Patent number: 9014254
    Abstract: Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Eugene R. Atwood, Matthew B. Baecher, Minhan Chen, Hayden C. Cranford, Jr., William R. Kelly, Todd M. Rasmus
  • Publication number: 20140376603
    Abstract: Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 25, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: EUGENE R. ATWOOD, MATTHEW B. BAECHER, MINHAN CHEN, HAYDEN C. CRANFORD, Jr., WILLIAM R. KELLY, TODD M. RASMUS
  • Patent number: 8767531
    Abstract: A communications link of multiple parallel communications lines includes at least one redundant line. In a first aspect, the lines are periodically recalibrated one at a time while the others carry functional data. If a fault is detected, the faulty line is disabled and the remaining previously calibrated lines transmit functional data. In a second aspect, impending line malfunction is detected from anomalies during calibration. In a third aspect, line malfunction is detected from receiver circuit output by determining a logical lane upon which each detected error occurs, and by mapping the logical lane to a physical line currently carrying the logical lane data.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Frank D. Ferraiolo, William R. Kelly, Robert J. Reese, Susan M. Rubow, Michael B. Spear
  • Publication number: 20140149629
    Abstract: Methods for detecting one or more signals at a PCI Express interface includes receiving, a signal by a receiver at the PCI Express interface. The methods further include identifying one or more data sampling points to set an amplitude threshold. Further, the method includes comparing an amplitude of the received signal with the amplitude threshold. The method also includes confirming that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The method also includes disabling a signal detector of the PCI Express interface to save power. The signal detector is configured to detect one or more low frequency signals; and testing whether the detected signal is correct.
    Type: Application
    Filed: February 28, 2013
    Publication date: May 29, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hayden C. Cranford, JR., Daniel M. Dreps, William R. Kelly
  • Publication number: 20140149627
    Abstract: A system for detecting one or more signals at a PCI Express interface includes a receiver configured to receive a signal at the PCI Express interface, and a peak detector configured to detect one or more signals based on level sensing, and identify one or more data sampling points to set an amplitude threshold. A comparator is configured to compare an amplitude of the received signal with the amplitude threshold, and a processor is configured to confirm that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The processor is also configured to disable a signal detector that can detect one or more low frequency signals. The system also includes a tester configured to test whether the detected signal is correct.
    Type: Application
    Filed: November 26, 2012
    Publication date: May 29, 2014
    Applicant: International Business Machines Corporation
    Inventors: Hayden C. Cranford, JR., Daniel M. Dreps, William R. Kelly
  • Patent number: 8401135
    Abstract: A serial data receiver includes an amplitude path including a first signal conditioner that adds a first offset or subtracts a second offset based on a selection input, a preamp configured to receive a signal from a transmitter and provide an input signal to the amplitude path, an amplitude latch coupled to the amplitude path, a data latch having a data output and a decision feedback equalization (DFE) logic block coupled to the first conditioning element and the data output and configured to generate the selection output based on the data output of the data latch.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: March 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Troy J. Beukema, William R. Kelly, Michael A. Sorna, Daniel W. Storaska
  • Publication number: 20120151247
    Abstract: A communications link of multiple parallel communications lines includes at least one redundant line. In a first aspect, the lines are periodically recalibrated one at a time while the others carry functional data. If a fault is detected, the faulty line is disabled and the remaining previously calibrated lines transmit functional data. In a second aspect, impending line malfunction is detected from anomalies during calibration. In a third aspect, line malfunction is detected from receiver circuit output by determining a logical lane upon which each detected error occurs, and by mapping the logical lane to a physical line currently carrying the logical lane data.
    Type: Application
    Filed: June 14, 2011
    Publication date: June 14, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Frank D. Ferraiolo, William R. Kelly, Robert J. Reese, Susan M. Rubow, Michael B. Spear
  • Patent number: 8139700
    Abstract: A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpolated output clock phase. An interpolated output clock phase is delayed to form a clock for a measurement device. Two or more adjusted input signals are measured on a measurement device over a range of interpolated output clock phases. Errors are determined on the in-phase clock and the quadrature clock using sampled information from the measurement device. The in-phase clock and the quadrature clock are adapted using determined error information.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Troy J. Beukema, Steven M. Clements, Chun-Ming Hsu, William R. Kelly, Elizabeth M. May, Sergey V. Rylov
  • Publication number: 20110188566
    Abstract: A serial data receiver includes an amplitude path including a first signal conditioner that adds a first offset or subtracts a second offset based on a selection input, a preamp configured to receive a signal from a transmitter and provide an input signal to the amplitude path, an amplitude latch coupled to the amplitude path, a data latch having a data output and a decision feedback equalization (DFE) logic block coupled to the first conditioning element and the data output and configured to generate the selection output based on the data output of the data latch.
    Type: Application
    Filed: February 2, 2010
    Publication date: August 4, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Troy J. Beukema, William R. Kelly, Michael A. Sorna, Daniel W. Storaska