Abstract: A subband channelizer for randomly spaced frequency groups includes: a first-stage channelizer configured to channelize a wideband input into a plurality of intermediate subbands, at least two of the plurality of intermediate subbands being partially overlapped; and a plurality of second-stage channelizers each configured to generate one or more final subbands from one of the plurality of intermediate subbands, wherein the intermediate subbands have wider bandwidth than the final subbands.

Abstract: A system and method for decoding an intended transmission includes a user device that receives a downlink transmission containing a user signal intended for the user device and one or more interfering user signals directed to one or more other user devices. The user device obtains power stacking information that includes a power level for each of the user signals contained in the received downlink transmission. A channel is estimated using pilot signals in the downlink transmission. Each interfering user signal contained in the downlink transmission is demodulated and decoded using the power stacking information. The user device removes all interfering user signals from the received downlink transmission to obtain the user signal intended for the user device.

Abstract: A system and method for decoding an intended transmission includes a user device that receives a downlink transmission containing a user signal intended for the user device and one or more interfering user signals directed to one or more other user devices. The user device obtains power stacking information that includes a power level for each of the user signals contained in the received downlink transmission. A channel is estimated using pilot signals in the downlink transmission. Each interfering user signal contained in the downlink transmission is demodulated and decoded using the power stacking information. The user device removes all interfering user signals from the received downlink transmission to obtain the user signal intended for the user device.

Abstract: A node processor and method for performing matrix operations includes storing, in memory, non-zero matrix elements of a first sparse matrix, non-zero matrix elements of a second sparse matrix, and matrix elements of a sparse results matrix mapped to the node processor. A matrix communications module exchanges with other node processors, non-zero matrix elements of one or more of the first sparse matrix, second sparse matrix, and sparse results matrix. An arithmetic logic unit generates partial results based on the non-zero matrix elements of the first sparse matrix and on the non-zero matrix elements of the second sparse matrix stored in memory. The arithmetic logic unit further generates a final value for each matrix element of the sparse results matrix mapped to the node processor based on the partial results generated by the arithmetic logic unit and on partial results received from the other node processors.

Abstract: A Doppler radar system that avoids blind ranges, range ambiguities, blind speed and/or Doppler ambiguities. Pulse width, repetition interval and pulse type are varied from pulse to pulse within a coherent processing interval.

Abstract: A node processor and method for performing matrix operations includes storing, in memory, non-zero matrix elements of a first sparse matrix, non-zero matrix elements of a second sparse matrix, and matrix elements of a sparse results matrix mapped to the node processor. A matrix communications module exchanges with other node processors, non-zero matrix elements of one or more of the first sparse matrix, second sparse matrix, and sparse results matrix. An arithmetic logic unit generates partial results based on the non-zero matrix elements of the first sparse matrix and on the non-zero matrix elements of the second sparse matrix stored in memory. The arithmetic logic unit further generates a final value for each matrix element of the sparse results matrix mapped to the node processor based on the partial results generated by the arithmetic logic unit and on partial results received from the other node processors.

Abstract: A parallel multiprocessor system includes a packet-switching communication network comprising a plurality of processor nodes operating concurrently in parallel. Each processor node generates messages to be sent simultaneously to a plurality of other processor nodes in the communication network. Each message is divided into a plurality of packets having a common destination processor node. Each processor node has an arbiter that determines an order in which to forward the packets onto the network toward their destination processor nodes and a network interface that sends the packets onto the network in accordance with the determined order. The determined order operates to substantially avoid sending consecutive packets from a given source processor node to a given destination processor node and to randomize the destination processor nodes of those packets presently traversing the communication network.

Abstract: A multiprocessor system and method for performing matrix operations includes multiple processors cooperatively performing a sparse matrix operation. Distributed among the processors are non-zero matrix elements of first and second sparse matrices. Mapped across the processors are the matrix elements of a results matrix. Each processor receives, from the other processors, non-zero matrix elements of the first matrix that had been distributed to those other processors and generates partial results based on the received non-zero matrix elements of the first matrix and on the non-zero matrix elements of the second matrix distributed to that processor. Each processor receives those partial results generated by other processors and associated with the matrix elements of the results matrix mapped to that processor.

Abstract: A parallel multiprocessor system includes a packet-switching communication network comprising a plurality of processor nodes operating concurrently in parallel. Each processor node generates messages to be sent simultaneously to a plurality of other processor nodes in the communication network. Each message is divided into a plurality of packets having a common destination processor node. Each processor node has an arbiter that determines an order in which to forward the packets onto the network toward their destination processor nodes and a network interface that sends the packets onto the network in accordance with the determined order. The determined order operates to substantially avoid sending consecutive packets from a given source processor node to a given destination processor node and to randomize the destination processor nodes of those packets presently traversing the communication network.

Abstract: A Doppler radar system that avoids blind ranges, range ambiguities, blind speed and/or Doppler ambiguities. Pulse width, repetition interval and pulse type are varied from pulse to pulse within a coherent processing interval.

Abstract: A signal-linearization system and method reduces nonlinear distortions in a digitized signal generated by an analog-to-digital converter (ADC) when converting an analog input signal from analog to digital form. A signal adder adds a dither waveform to the analog input signal. An ADC includes sample-and-hold (S/H) circuitry and quantizer circuitry. The ADC converts the analog input signal with the added dither waveform into a digitized signal. The dither waveform operates to suppress nonlinear distortions attributed to the quantizer circuitry. A linearizer processor performs nonlinear equalization (NLEQ) on the digitized signal to suppress nonlinear distortions attributed to the S/H circuitry. A dither waveform removal module removes a digital counterpart of the dither waveform from the digitized signal.

Abstract: In conventional pulse compression processing, sidelobes from strong return signals may hide correlation peaks associated with weaker return signals. Example embodiments include methods of mitigating this near/far interference by weighting a received return signal or corresponding reference signal based the return signal's time of arrival, then performing pulse compression using the weighted signal to produce a correlation peak that is not hidden by sidelobes from another return. Multi-frequency processing can also be used to reduce the pulse width of the transmitted pulses and received return signals, thereby mitigating near/far interference by decreasing the overlap between signals from nearby targets. Weighting can be combined with multi-frequency pulse transmission and reception to further enhance the fidelity of the processed correlation peak. Weighting and multi-frequency processing also enable higher duty cycles than are possible with conventional pulse compression radars.

Abstract: A sorter system includes a clock continuously generating a series of clock signals, a systolic array circuit, and control circuitry in communication with serial access memory that stores data items of a sequence to be sorted and with the systolic array circuit to supply thereto data items as input and to receive therefrom data items as output. The systolic array circuit includes at least one processing module and K?1 registers, where K is an integer value greater than two. Each processing module has at least one of the registers, each register for storing one data item. The control circuitry serially presents K data items for input to the systolic array circuit in synchronization with the clock signals. On the next clock cycle after the control circuitry presents to the systolic array circuit the last of the K data items, the data item of least value in the given subsequence is output.

Abstract: A signal-linearization system and method reduces nonlinear distortions in a digitized signal generated by an analog-to-digital converter (ADC) when converting an analog input signal from analog to digital form. A signal adder adds a dither waveform to the analog input signal. An ADC includes sample-and-hold (S/H) circuitry and quantizer circuitry. The ADC converts the analog input signal with the added dither waveform into a digitized signal. The dither waveform operates to suppress nonlinear distortions attributed to the quantizer circuitry. A linearizer processor performs nonlinear equalization (NLEQ) on the digitized signal to suppress nonlinear distortions attributed to the S/H circuitry. A dither waveform removal module removes a digital counterpart of the dither waveform from the digitized signal.

Abstract: A multiprocessor system and method for performing matrix operations includes multiple processors cooperatively performing a sparse matrix operation. Distributed among the processors are non-zero matrix elements of first and second sparse matrices. Mapped across the processors are the matrix elements of a results matrix. Each processor receives, from the other processors, non-zero matrix elements of the first matrix that had been distributed to those other processors and generates partial results based on the received non-zero matrix elements of the first matrix and on the non-zero matrix elements of the second matrix distributed to that processor. Each processor receives those partial results generated by other processors and associated with the matrix elements of the results matrix mapped to that processor.

Abstract: In conventional pulse compression processing, sidelobes from strong return signals may hide correlation peaks associated with weaker return signals. Example embodiments include methods of mitigating this near/far interference by weighting a received return signal or corresponding reference signal based the return signal's time of arrival, then performing pulse compression using the weighted signal to produce a correlation peak that is not hidden by sidelobes from another return. Multi-frequency processing can also be used to reduce the pulse width of the transmitted pulses and received return signals, thereby mitigating near/far interference by decreasing the overlap between signals from nearby targets. Weighting can be combined with multi-frequency pulse transmission and reception to further enhance the fidelity of the processed correlation peak. Weighting and multi-frequency processing also enable higher duty cycles than are possible with conventional pulse compression radars.

Abstract: Described are nonlinear filter processors having an array of polynomial nonlinear filters including a first polynomial nonlinear filter and a last polynomial nonlinear filter. The first polynomial nonlinear filter has an input terminal for receiving an input data sample. The polynomial nonlinear filters systolically pass the input data sample from the first polynomial nonlinear filter to the last polynomial nonlinear filter. Each polynomial nonlinear filter produces an output data sample based on the input data sample. In addition, each polynomial nonlinear filter other than the last polynomial nonlinear filter systolically passes the output data sample generated by that polynomial nonlinear filter to a neighboring polynomial nonlinear filter. Each polynomial nonlinear filter other than the first polynomial nonlinear filter sums a nonlinearly filtered input data sample produced by that polynomial nonlinear filter with the output data sample received from a neighboring polynomial nonlinear filter.

Abstract: A sorter system includes a clock continuously generating a series of clock signals, a systolic array circuit, and control circuitry in communication with serial access memory that stores data items of a sequence to be sorted and with the systolic array circuit to supply thereto data items as input and to receive therefrom data items as output. The systolic array circuit includes at least one processing module and K?1 registers, where K is an integer value greater than two. Each processing module has at least one of the registers, each register for storing one data item. The control circuitry serially presents K data items for input to the systolic array circuit in synchronization with the clock signals. On the next clock cycle after the control circuitry presents to the systolic array circuit the last of the K data items, the data item of least value in the given subsequence is output.

Abstract: Described is a finite impulse filter response (FIR) filter for use by signal processors. A demultiplexer receives input data samples at an input data rate. The FIR filter includes a plurality of computational units arranged in a systolic array of taps and phases. Each computational unit operates at an array clock rate that is slower than the input data rate. During each array clock cycle, the phases produce a plurality of output data samples that provides an output data rate equal to the input data rate. The FIR filters can thus support an output data rate equal to the input data rate although the input data rate exceeds the maximum clock speed of the processor. The FIR filter can also operate at a reduced array clock speed, while continuing to produce an output data rate equal to the input data rate, to increase the power efficiency of the processor.

Abstract: Described are nonlinear filter processors having an array of polynomial nonlinear filters including a first polynomial nonlinear filter and a last polynomial nonlinear filter. The first polynomial nonlinear filter has an input terminal for receiving an input data sample. The polynomial nonlinear filters systolically pass the input data sample from the first polynomial nonlinear filter to the last polynomial nonlinear filter. Each polynomial nonlinear filter produces an output data sample based on the input data sample. In addition, each polynomial nonlinear filter other than the last polynomial nonlinear filter systolically passes the output data sample generated by that polynomial nonlinear filter to a neighboring polynomial nonlinear filter. Each polynomial nonlinear filter other than the first polynomial nonlinear filter sums a nonlinearly filtered input data sample produced by that polynomial nonlinear filter with the output data sample received from a neighboring polynomial nonlinear filter.