Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements output by a processing resource and generate metadata to indicate a location of the zero value elements within the plurality of data elements.

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

Abstract: In one of its aspects, the present invention relates to a process for forming a flexible liquid-packaging pouch. This process improves fill-accuracy of the flowable material contained in the pouch. Specifically, the invention relates to a process for improving the fill-accuracy of a pouch by incorporating at least one stand-pipe in a balance tank that feeds the pouch with flowable material to be packaged. This invention also relates to such apparatus for improving the fill-accuracy of the flexible liquid-packaging pouch.

Abstract: This invention relates to a method for sealing film layers to form a sealed portion and a notch within the sealed portion, comprising: providing film layers between sealing jaws comprising a heat sealing element, with a sealing face having a length and a protrusion extending partly along the length of its sealing face; inducing a temperature gradient along the of sealing face length, wherein the temperature proximate to the protrusion is higher than at a distance from the protrusion; closing the jaws and simultaneously clamping the film at a location adjacent to the sealing face; holding the jaws closed for a period of time; and opening the jaws to release the layers of film.

Abstract: This invention relates to a method for sealing film layers to form a sealed portion and a notch within the sealed portion, comprising: providing film layers between sealing jaws comprising a heat sealing element, with a sealing face having a length and a protrusion extending partly along the length of its sealing face; inducing a temperature gradient along the of sealing face length, wherein the temperature proximate to the protrusion is higher than at a distance from the protrusion; closing the jaws and simultaneously clamping the film at a location adjacent to the sealing face; holding the jaws closed for a period of time; and opening the jaws to release the layers of film.

Abstract: This invention relates to a heat sealing element for use in a heat sealing jaw in cooperation with an opposing backing jaw for sealing layers of film together to form a sealed portion and a notch within the sealed portion, the heat sealing element comprising: a sealing face for pressing the layers of film together against the opposing backing jaw and forming the sealed portion, the sealing face having a protrusion for forming the notch within the sealed portion; and a clamping portion adjacent to the sealing face, the clamping portion being disposed at an orientation diverging from a plane along which the layers of film are sealed together.

Abstract: A heat sealing jaw for use in cooperation with an opposing backing jaw for sealing layers of film together is described. The heat sealing jaw may be suitable for forming an easy-open feature on a packaging pouch used to contain flowable material. In certain embodiments the heat sealing jaw comprises a jaw body, a heat sealing element secured to the jaw body, a support surface for clamping the layers of film together against the opposing backing jaw, and, a heat sink coupled to the heat sealing element for inducing a temperature gradient along a sealing face of the heat sealing element. The sealing face may have a protrusion for forming a notch within the layers of film. Related apparatuses and methods are also described.

Abstract: A heat sealing jaw for use in cooperation with an opposing backing jaw for sealing layers of film together is described. The heat sealing jaw may be suitable for forming an easy-open feature on a packaging pouch used to contain flowable material. In certain embodiments the heat sealing jaw comprises a jaw body, a heat sealing element secured to the jaw body, a support surface for clamping the layers of film together against the opposing backing jaw, and, a heat sink coupled to the heat sealing element for inducing a temperature gradient along a sealing face of the heat sealing element. The sealing face may have a protrusion for forming a notch within the layers of film. Related apparatuses and methods are also described.