Patents by Inventor William T. Lee

William T. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10262943
    Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: April 16, 2019
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
  • Patent number: 10128116
    Abstract: Efficient integrated sequential deposition of alternating layers of dielectric and conductor, for example oxide/metal or metal nitride, e.g., SiO2/TiN, in a single tool, and even in a single process chamber enhances throughput without compromising quality when directly depositing a OMOM stack with many layers. Conductor and dielectric film deposition of a stack of at least 20 conductor/dielectric film pairs in the same processing tool or chamber, without breaking vacuum between the film depositions, such that there is no substantial cross-contamination between the conductor and dielectric film depositions, can be achieved.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: November 13, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: William T. Lee, Bart J. van Schravendijk, David Charles Smith, Michal Danek, Patrick A. Van Cleemput, Ramesh Chandrasekharan
  • Publication number: 20180151503
    Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
    Type: Application
    Filed: January 23, 2018
    Publication date: May 31, 2018
    Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
  • Publication number: 20180108529
    Abstract: Efficient integrated sequential deposition of alternating layers of dielectric and conductor, for example oxide/metal or metal nitride, e.g., SiO2/TiN, in a single tool, and even in a single process chamber enhances throughput without compromising quality when directly depositing a OMOM stack with many layers. Conductor and dielectric film deposition of a stack of at least 20 conductor/dielectric film pairs in the same processing tool or chamber, without breaking vacuum between the film depositions, such that there is no substantial cross-contamination between the conductor and dielectric film depositions, can be achieved.
    Type: Application
    Filed: May 11, 2017
    Publication date: April 19, 2018
    Inventors: William T. Lee, Bart J. van Schravendijk, David Charles Smith, Michal Danek, Patrick A. Van Cleemput, Ramesh Chandrasekharan
  • Patent number: 9875968
    Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: January 23, 2018
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
  • Publication number: 20170162512
    Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
    Type: Application
    Filed: February 24, 2017
    Publication date: June 8, 2017
    Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
  • Patent number: 9583386
    Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: February 28, 2017
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
  • Patent number: 9418889
    Abstract: A dielectric diffusion barrier is deposited on a substrate that has a via and an overlying trench etched into an exposed layer of inter-layer dielectric, wherein there is exposed metal from the underlying interconnect at the bottom of the via. In order to provide a conductive path from the underlying metallization layer to the metallization layer that is being formed over it, the dielectric diffusion barrier is formed selectively on the inter-layer dielectric and not on the exposed metal at the bottom of the via. In one example a dielectric SiNC diffusion barrier layer is selectively deposited on the inter-layer dielectric using a remote plasma deposition and a precursor that contains both silicon and nitrogen atoms. Generally, a variety of dielectric diffusion barrier materials with dielectric constants of between about 3.0-20.0 can be selectively formed on inter-layer dielectric.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: August 16, 2016
    Assignee: Lam Research Corporation
    Inventors: Thomas Weller Mountsier, Hui-Jung Wu, Bhadri N. Varadarajan, Nagraj Shankar, William T. Lee
  • Publication number: 20160118296
    Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
    Type: Application
    Filed: October 2, 2015
    Publication date: April 28, 2016
    Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
  • Publication number: 20150380302
    Abstract: A dielectric diffusion barrier is deposited on a substrate that has a via and an overlying trench etched into an exposed layer of inter-layer dielectric, wherein there is exposed metal from the underlying interconnect at the bottom of the via. In order to provide a conductive path from the underlying metallization layer to the metallization layer that is being formed over it, the dielectric diffusion barrier is formed selectively on the inter-layer dielectric and not on the exposed metal at the bottom of the via. In one example a dielectric SiNC diffusion barrier layer is selectively deposited on the inter-layer dielectric using a remote plasma deposition and a precursor that contains both silicon and nitrogen atoms. Generally, a variety of dielectric diffusion barrier materials with dielectric constants of between about 3.0-20.0 can be selectively formed on inter-layer dielectric.
    Type: Application
    Filed: June 17, 2015
    Publication date: December 31, 2015
    Inventors: Thomas Weller Mountsier, Hui-Jung Wu, Bhadri N. Varadarajan, Nagraj Shankar, William T. Lee
  • Patent number: 9184060
    Abstract: The embodiments herein relate to methods, apparatus, and systems for forming recessed features at high aspect ratios. Often, such features are formed in the context of fabricating a vertical NAND (VNAND) memory device. Various disclosed embodiments relate to process flows that involve depositing and shaping sacrificial posts on a metal seed layer that covers an underlying stack of materials, electroplating or electroless plating metal hard mask material around the sacrificial posts, removing the sacrificial posts, and etching the underlying stack of materials to form a high aspect ratio recessed feature.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: November 10, 2015
    Assignee: Lam Research Corporation
    Inventor: William T. Lee
  • Patent number: 9006893
    Abstract: An electronic device which in one embodiment comprises a metallization stack is provided. The metallization stack comprises a barrier metal deposited electrolessly and a substantially gold-free wetting layer deposited electrolessly. Additionally, the barrier metal contacts the wetting layer, where the wetting layer is wettable by solder.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: April 14, 2015
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, William T. Lee, Fritz Redeker
  • Patent number: 8828863
    Abstract: A method for providing metal filled features in a layer is provided. A nonconformal metal seed layer is deposited on tops, sidewalls, and bottoms of the features, wherein more seed layer is deposited on tops and bottoms of features than sidewalls. The metal seed layer are etched back on tops, sidewalls, and bottoms of the features, wherein some metal seed layer remains on tops and bottoms of the features. Deposition on the seed layer on tops of the features is suppressed. An electroless “bottom up” deposition of metal is provided to fill the features.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: September 9, 2014
    Assignee: Lam Research Corporation
    Inventors: William T. Lee, Xiaomin Bin
  • Patent number: 8673779
    Abstract: A method of filling of vias and trenches in a dual damascene structure with a filling comprising copper or copper alloy is provided. An electroless deposition filling of the vias with a via filling comprising copper or copper alloy is provided. A trench barrier layer is formed over the via filling with a trench barrier layer comprising Mn or Al. The trench barrier layer is annealed at a temperature that causes a component of the trench barrier layer to pass into the via filling. The trenches are filled with a trench filling comprising copper or copper alloy.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: March 18, 2014
    Assignee: Lam Research Corporation
    Inventors: Hyungsuk A. Yoon, William T. Lee
  • Publication number: 20140054776
    Abstract: A method of making an electronic device which in one embodiment comprises providing a substrate, electrolessly depositing a barrier metal at least on portions of the substrate, and using wet chemistry such as electroless deposition to deposit a substantially gold-free wetting layer having solder wettability onto the barrier metal. An electronic device which in one embodiment comprises a metallization stack. The metallization stack comprises a barrier metal deposited electrolessly and a substantially gold-free wetting layer deposited on the barrier metal, and the wetting layer is wettable by solder.
    Type: Application
    Filed: August 22, 2013
    Publication date: February 27, 2014
    Applicant: Lam Research Corporation
    Inventors: Artur KOLICS, William T. LEE, Fritz REDEKER
  • Patent number: 8518815
    Abstract: A method of making an electronic device which in one embodiment comprises providing a substrate, electrolessly depositing a barrier metal at least on portions of the substrate, and using wet chemistry such as electroless deposition to deposit a substantially gold-free wetting layer having solder wettability onto the barrier metal. An electronic device which in one embodiment comprises a metallization stack. The metallization stack comprises a barrier metal deposited electrolessly and a substantially gold-free wetting layer deposited on the barrier metal, and the wetting layer is wettable by solder.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: August 27, 2013
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, William T. Lee, Fritz Redeker
  • Publication number: 20120007239
    Abstract: A method of making an electronic device which in one embodiment comprises providing a substrate, electrolessly depositing a barrier metal at least on portions of the substrate, and using wet chemistry such as electroless deposition to deposit a substantially gold-free wetting layer having solder wettability onto the barrier metal. An electronic device which in one embodiment comprises a metallization stack. The metallization stack comprises a barrier metal deposited electrolessly and a substantially gold-free wetting layer deposited on the barrier metal, and the wetting layer is wettable by solder.
    Type: Application
    Filed: July 7, 2010
    Publication date: January 12, 2012
    Inventors: Artur Kolics, William T. Lee, Fritz Redeker
  • Patent number: 6557967
    Abstract: A method for forming a chamber or nozzle structure in a substrate. The chamber is formed by first creating a surface feature, such as a pit or trench, on the surface of the substrate. A layer of resist is applied to the sidewall of the surface feature and the substrate is isotropically etched such that the etch works back up the inside of the resist on the surface feature sidewall to form a re-entrant angle between the surface feature sidewall and the top of the chamber wall. This results in a chamber that is wider than the opening between the sidewalls of the surface feature. An anisotropic etch step may be performed before or after the isotropic etch step or steps to control the final shape of the chamber.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: May 6, 2003
    Assignee: Applied Materials Inc.
    Inventor: William T. Lee
  • Patent number: 6235634
    Abstract: The invention provides an apparatus and method for performing a process on a substrate. At least two types of structures may be used to provide a flow path for a substrate so that the substrate may be moved from one processing or loading position to another. The first is a conveyor. The second is a track. The flow path may be a closed continuous loop. Each processing island has a valve for introduction and extraction of the substrate into and out of an interior of the island. The processing island may include load locks, and may include in conjunction therewith an inspection station, a CVD chamber, a PECVD chamber, a PVD chamber, a post-anneal chamber, a cleaning chamber, a descumming chamber, an etch chamber, or a combination of such chambers.
    Type: Grant
    Filed: May 20, 1998
    Date of Patent: May 22, 2001
    Assignee: Applied Komatsu Technology, Inc.
    Inventors: John M. White, Robert B. Conner, Kam S. Law, Norman L. Turner, William T. Lee, Shinichi Kurita
  • Patent number: 6171510
    Abstract: A method for forming a chamber or nozzle structure in a substrate. The chamber is formed by first creating a surface feature, such as a pit or trench, on the surface of the substrate. A layer of resist is applied to the sidewall of the surface feature and the substrate is isotropically etched such that the etch works back up the inside of the resist on the surface feature sidewall to form a re-entrant angle between the surface feature sidewall and the top of the chamber wall. This results in a chamber that is wider than the opening between the sidewalls of the surface feature. An anisotropic etch step may be performed before or after the isotropic etch step or steps to control the final shape of the chamber.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: January 9, 2001
    Assignee: Applied Materials Inc.
    Inventor: William T. Lee