Abstract: Disclosed herein are crystalline forms of L-ornithine phenyl acetate and methods of making the same. The crystalline form may, in some embodiments, be Forms I, II, III and V, or mixtures thereof. The crystalline forms may be formulated for treating subjects with liver disorders, such as hepatic encephalopathy. Accordingly, some embodiments include formulations and methods of administering L-ornithine phenyl acetate.

Abstract: There is provided a system and method for rule-based dynamic server-side streaming manifest files. There is provided a method comprising receiving a request to provide a first video content for playback, evaluating a plurality of rules for the first video content, generating a dynamic manifest file referencing the first video content, and providing the dynamic manifest file in response to the request, thereby enabling an application to playback the first video content for output on a display by interpreting the dynamic manifest file. The rules may implement various features such as dynamic advertisement insertion, load balancing, client customization, user and device targeting, enhanced security mechanisms, global announcements, and others. As streaming protocols are widely supported by default on many client platforms, the dynamic manifest files can be utilized in a user friendly and transparent manner compared to client-side solutions requiring cumbersome client software installations.

Abstract: A depilatory article comprising a substrate and an aqueous depilatory composition, the aqueous depilatory composition being in physical contact with the substrate, forming a coated area of the substrate and comprising a thioglycolate salt and a silicate.

Abstract: A depilatory article comprising a water impermeable substrate and an aqueous depilatory composition, the aqueous depilatory composition being in physical contact with the water impermeable substrate and comprising a keratin reducing agent and water in an amount of at least 40% by weight of the aqueous depilatory composition; wherein the aqueous depilatory composition forms a covered region of the water impermeable substrate and wherein the keratin reducing agent is present in an amount per unit area of the covered region of from 1×10?7 mol/cm2 to 4×10?5 mol/cm2 from 1×10?6 mol/cm2 to 2×10?5 mol/cm2, preferably from 5×10?6 mol/cm2 to 1.5×10?5 mol/cm2 and more preferably from 7×10?6 mol/cm2 to 1.

Abstract: A depilatory article comprising a water impermeable substrate and an aqueous depilatory composition, the aqueous depilatory composition being in physical contact with the water impermeable substrate, forming a coated region of the water impermeable substrate and comprising a thioglycolate salt, a water-soluble or colloid-forming silicate, and a divalent metal cation.

Abstract: A depilatory article comprising a substrate and an aqueous depilatory composition, the aqueous depilatory composition being in physical contact with the substrate, forming a coated region of the substrate and comprising a thioglycolate salt and silica.

Abstract: A depilatory article comprising a substrate and an aqueous depilatory composition, the aqueous depilatory composition being in physical contact with the substrate and comprising a keratin reducing agent and one or more monovalent cations; wherein the aqueous depilatory composition forms a coated region of the substrate; and wherein the amount of monovalent cations per unit area of said coated region is from 6×10?7 mol/cm2 to 6×10?6 mol/cm2, preferably from 1.5×10?6 mol/cm2 to 4.5×10?6 mol/cm2 and more preferably from 2.25×10?6 mol/cm2 to 3.75×10?6 mol/cm2.

Abstract: Disclosed herein are crystalline forms of L-ornithine phenyl acetate and methods of making the same. The crystalline form may, in some embodiments, be Forms I, II, III and V, or mixtures thereof. The crystalline forms may be formulated for treating subjects with liver disorders, such as hepatic encephalopathy. Accordingly, some embodiments include formulations and methods of administering L-ornithine phenyl acetate.

Abstract: Systems and methods for determining active constraints in a surface facility network, which include the use of slack variables and multipliers in system equations to eliminate the extraneous (inactive) constraints.

Abstract: Systems and methods for parallel ILU factorization in distributed sparse linear systems, which utilize a method for ordering nodes underlying the equations in the system(s) and reducing processing time.

Abstract: Systems and methods for determining active constraints in a surface facility network, which include the use of slack variables and multipliers in system equations to eliminate the extraneous (inactive) constraints.

Abstract: Polymorphs and pharmaceutical formulations of 17-allylamino-17-demethoxygeldanamycin (17-AAG).

Abstract: Machine vibration baselines are synthesized without averaging historical vibration data. Instead machinery configuration information is used, including data about the machine train, the machine's rotating components, and the machine speeds. For each component being considered, a plurality of parameters is identified for deriving baseline portions. The parameters for one component are used to identify baseline vibration amplitude floor values, vibration amplitudes at frequencies corresponding to various harmonics of a rotational speed, and vibration amplitudes corresponding to forcing frequencies and their harmonics/sidebands. Parameters for other components also may be used to identify amplitudes at harmonic frequencies and forcing frequencies.

Abstract: This invention relates to antimicrobial polyurethane foams and to a method of making antimicrobial polyurethane foams. The invention also relates to the use of such foams in the production of medical devices and pharmaceutical compositions.

Abstract: Systems and methods for determining active constraints in a surface facility network, which include the use of slack variables and multipliers in system equations to eliminate the extraneous (inactive) constraints.

Abstract: Polymorphs and pharmaceutical formulations of 17-allylamino-17-demethoxy-geldanamycin (17-AAG).

Abstract: A logic simulation processor stores in a shift register intermediate values generated during the logic simulation. The simulation processor includes multiple processor units and an interconnect system that communicatively couples the processor units to each other. Each of the processor units includes a processor element configurable to simulate at least a logic gate, and a shift register associated with the processor element. The shift register includes multiple entries to store the intermediate values, and is coupled to receive the output of the processor element. Each of the processor units further includes one or more multiplexers for selecting one of the entries of the shift register as outputs to be coupled to the interconnect system. Each of the processor units may further include a local memory for storing data from, and loading the data to, the simulation processor.

Abstract: In one aspect, the present invention overcomes the limitations of the prior art by provident a logic simulation ;system that uses a VLIW simulation processor with many parallel processor elements to accelerate the simulation of synthesizable tasks but that also supports non-synthesizable tasks and/or branching. In one approach, the VLIW simulation processor is based on an architecture that does not have an on-chip instruction cache. Instead, VLIW instruction words stream in directly from a program memory and the individual processor elements are programmed continuously based on the instruction words. This also allows the efficient implementation of side-entrance jumps, where a region of code can be entered in the middle of the region rather than always requiring entrance from the top. In another aspect, non-synthesizable tasks can be efficiently handled by exception handlers.

Abstract: A processor system comprising a processor and a memory system with a high data transfer rate and low average power consumption of related I/O activity. The processor system may be disposed on a single circuit board. One embodiment of a disclosed system includes a processor system that comprises a processor device, a memory device and a circuit board. The circuit board includes a substrate, electrical contacts, and interconnection lines between the contacts. The electrical contacts of the circuit board may be coupled to electrical contacts on the processor device and the memory device. The interconnection lines communicate signals, such as data or instructions, between the electrical contacts of the memory device and the process device at least 200 billion bits per second while related input/output activity of the processor and the memory consumes an average power less than ten watts.

Abstract: A hardware-accelerated simulator includes a storage memory and a program memory that are separately accessible by the simulation processor. The program memory stores instructions to be executed in order to simulate the chip. The storage memory is used to simulate the user memory. Since the program memory and storage memory are separately accessible by the simulation processor, the simulation of reads and writes to user memory does not block the transfer of instructions between the program memory and the simulation processor, thus increasing the speed of simulation. In one aspect, user memory addresses are mapped to storage memory addresses by adding a fixed, predetermined offset to the user memory address. Thus, no address translation is required at run-time.