Patents by Inventor William Weilun HONG

William Weilun HONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210272818
    Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.
    Type: Application
    Filed: May 18, 2021
    Publication date: September 2, 2021
    Inventors: Yi-Sheng LIN, Chi-Jen LIU, Chi-Hsiang SHEN, Te-Ming KUNG, Chun-Wei HSU, Chia-Wei HO, Yang-Chun CHENG, William Weilun HONG, Liang-Guang CHEN, Kei-Wei CHEN
  • Patent number: 11094555
    Abstract: The current disclosure describes a metal surface chemical mechanical polishing technique. A complex agent or micelle is included in the metal CMP slurry. The complex agent bonds with the oxidizer contained in the CMP slurry to form a complex, e.g., a supramolecular assembly, with an oxidizer molecule in the core of the assembly and surrounded by the complex agent molecule(s). The formed complexes have an enlarged size.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wei Hsu, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, William Weilun Hong, Chi-Hsiang Shen, Chia-Wei Ho, Yang-Chun Cheng
  • Publication number: 20210225657
    Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.
    Type: Application
    Filed: April 1, 2021
    Publication date: July 22, 2021
    Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
  • Patent number: 11069533
    Abstract: A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Chien Hou, Yu-Ting Yen, Cheng-Yu Kuo, Chih Hung Chen, William Weilun Hong, Kei-Wei Chen
  • Patent number: 11037799
    Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yi-Sheng Lin, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, Te-Ming Kung, William Weilun Hong, Chi-Hsiang Shen, Chia-Wei Ho, Chun-Wei Hsu, Yang-Chun Cheng
  • Patent number: 10971370
    Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
  • Publication number: 20210020449
    Abstract: A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 21, 2021
    Inventors: Te-Chien Hou, Yu-Ting Yen, Cheng-Yu Kuo, Chih Hung Chen, William Weilun Hong, Kei-Wei Chen
  • Publication number: 20200365413
    Abstract: A method includes forming a film over a substrate; increasing a surface roughness of the film; and planarizing the film using a first chemical mechanical planarization (CMP) process after increasing the surface roughness.
    Type: Application
    Filed: May 17, 2019
    Publication date: November 19, 2020
    Inventors: Po-Chin Nien, Gang Huang, William Weilun Hong
  • Publication number: 20200279751
    Abstract: The current disclosure describes a metal surface chemical mechanical polishing technique. A complex agent or micelle is included in the metal CMP slurry. The complex agent bonds with the oxidizer contained in the CMP slurry to form a complex, e.g., a supramolecular assembly, with an oxidizer molecule in the core of the assembly and surrounded by the complex agent molecule(s). The formed complexes have an enlarged size.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Chun-Wei Hsu, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, William Weilun Hong, Chi-Hsiang Shen, Chia-Wei Ho, Yang-Chun Cheng
  • Patent number: 10692732
    Abstract: The current disclosure describes a metal surface chemical mechanical polishing technique. A complex agent or micelle is included in the metal CMP slurry. The complex agent bonds with the oxidizer contained in the CMP slurry to form a complex, e.g., a supramolecular assembly, with an oxidizer molecule in the core of the assembly and surrounded by the complex agent molecule(s). The formed complexes have an enlarged size.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wei Hsu, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, William Weilun Hong, Chi-hsiang Shen, Chia-Wei Ho, Yang-chun Cheng
  • Publication number: 20200126803
    Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.
    Type: Application
    Filed: December 19, 2019
    Publication date: April 23, 2020
    Inventors: Wan-Chun Pan, William Weilun Hong, Ying-Tsung Chen
  • Publication number: 20200118827
    Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
  • Publication number: 20200105668
    Abstract: A semiconductor device includes a first dielectric layer over a substrate, the first dielectric layer including a first dielectric material extending from a first side of the first dielectric layer distal from the substrate to a second side of the first dielectric layer opposing the first side; a second dielectric layer over the first dielectric layer; a conductive line in the first dielectric layer, the conductive line including a first conductive material, an upper surface of the conductive line being closer to the substrate than an upper surface of the first dielectric layer; a metal cap in the first dielectric layer, the metal cap being over and physically connected to the conductive line, the metal cap including a second conductive material different from the first conductive material; and a via in the second dielectric layer and physically connected to the metal cap, the via including the second conductive material.
    Type: Application
    Filed: July 29, 2019
    Publication date: April 2, 2020
    Inventors: Chia-Wei Ho, Chun-Wei Hsu, Chi-Hsiang Shen, Chi-Jen Liu, Yi-Sheng Lin, Yang-Chun Cheng, William Weilun Hong, Liang-Guang Chen, Kei-Wei Chen
  • Publication number: 20200098591
    Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.
    Type: Application
    Filed: May 1, 2019
    Publication date: March 26, 2020
    Inventors: Yi-Sheng Lin, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, Te-Ming Kung, William Weilun Hong, Chi-Hsiang Shen, Chia-Wei Ho, Chun-Wei Hsu, Yang-Chun Cheng
  • Publication number: 20200098590
    Abstract: The current disclosure describes a metal surface chemical mechanical polishing technique. A complex agent or micelle is included in the metal CMP slurry. The complex agent bonds with the oxidizer contained in the CMP slurry to form a complex, e.g., a supramolecular assembly, with an oxidizer molecule in the core of the assembly and surrounded by the complex agent molecule(s). The formed complexes have an enlarged size.
    Type: Application
    Filed: September 21, 2018
    Publication date: March 26, 2020
    Inventors: Chun-Wei Hsu, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, William Weilun Hong, Chi-hsiang Shen, Chia-Wei Ho, Yang-chun Cheng
  • Patent number: 10541139
    Abstract: A method of forming a semiconductor device includes forming fins on a substrate, depositing a gate layer having a first material on the fins, and depositing a sacrificial layer having a second material on the gate layer. The method further includes removing a first portion of the sacrificial layer using a first slurry or etchant having a first selectivity of second material to first material. The method further includes removing a first portion of the gate layer and a second portion of the sacrificial layer using a second slurry or etchant having a second selectivity of second material to first material to form a planarized gate layer. The first selectivity is greater than the second selectivity. An example benefit includes reduced dependency of the gate layer planarization process on underlying structure density and reduced variation in thickness of the gate layer on device structures across a wafer.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: January 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
  • Patent number: 10522365
    Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Chun Pan, William Weilun Hong, Ying-Tsung Chen
  • Patent number: 10510552
    Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manfacturing Company, Ltd.
    Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
  • Patent number: 10068988
    Abstract: A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the polysilicon layer to change its removal rate, thereby forming a doped layer, and removing the doped layer in the first region to expose the polysilicon layer in the first region and leaving at least a portion of the doped layer in the second region. The method also includes removing the exposed polysilicon layer in the first region at a first removal rate and the doped layer in the second region at a second removal rate, the polysilicon layer in the second region being exposed after the doped layer in the second region is removed, and removing the polysilicon layer in the first region and the second region at a third removal rate and a fourth removal rate, respectively.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: September 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: William Weilun Hong, Po-Chin Nien, Ying-Tsung Chen
  • Publication number: 20180240679
    Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.
    Type: Application
    Filed: April 20, 2018
    Publication date: August 23, 2018
    Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen