Abstract: A signal processor includes a frequency generator that employs a direct digital synthesizer (DDS) to generate a first local oscillator (LO) signal with a variable first LO frequency. The signal processor also includes an oscillator generating a second LO signal having a second LO frequency. The DDS employs programmable frequency control word and a sampling clock signal having a variable sampling clock frequency that is derived from the second LO frequency, to generate a DDS output signal from which the first LO signal is produced. The variable sampling clock frequency and the programmable frequency control word are selected to avoid crossing spurs in the frequency spectrum of the DDS output signal.

Abstract: A device includes: a plurality of sampling phase detectors, each receiving a sampling signal and a VCO output signal and in response thereto outputting a beat signal representing a frequency and phase difference between the VCO output signal and the sampling signal; a frequency/phase detector receiving a reference signal and a combined beat signal produced by combining the beat signals, and in response thereto producing an error signal representing a phase difference between the reference signal and the combined beat signal; a loop integrator receiving the error signal and in response thereto producing the VCO control signal; a power detector detecting a power level of the combined beat signal; and at least one offset voltage generator adjusting a value of a bias voltage in response to the detected power level of the combined beat signal, and applying the adjusted bias voltage to one of the sampling phase detectors.

Abstract: A device includes: a plurality of sampling phase detectors, each receiving a sampling signal and a VCO output signal and in response thereto outputting a beat signal representing a frequency and phase difference between the VCO output signal and the sampling signal; a frequency/phase detector receiving a reference signal and a combined beat signal produced by combining the beat signals, and in response thereto producing an error signal representing a phase difference between the reference signal and the combined beat signal; a loop integrator receiving the error signal and in response thereto producing the VCO control signal; a power detector detecting a power level of the combined beat signal; and at least one offset voltage generator adjusting a value of a bias voltage in response to the detected power level of the combined beat signal, and applying the adjusted bias voltage to one of the sampling phase detectors.

Abstract: A measurement technique that provides a full solution to the gated local oscillator sweep measurement and improves the accuracy of signal analyzers in gated sweep mode by pre-sweeping the local oscillator at the beginning of a gate pulse and over-sweeping the local oscillator at the end of each gate pulse.

Abstract: A measurement technique that provides a full solution to the gated local oscillator sweep measurement and improves the accuracy of signal analyzers in gated sweep mode by pre-sweeping the local oscillator at the beginning of a gate pulse and over-sweeping the local oscillator at the end of each gate pulse.

Abstract: A vector network analysis system and a method of measuring use offset stimulus signals to stimulate a balanced device under test (DUT) to determine performance parameters. The system includes an offset stimulus source that provides a plurality of stimulus signals and a vector network analyzer. At least one stimulus signal is offset from another stimulus signal of the plurality in one or both of frequency and time-varying phase. The offset stimulus source includes a first signal source and a second signal source that respectively provides the offset stimulus signals. The method of measuring includes generating the offset stimulus signals and applying the offset stimulus signals to a balanced port of the DUT to stimulate the DUT. The performance parameters are determined from measurements of the offset stimulus signals and one or more response signals from the stimulated DUT.

Abstract: This invention adds a non-linear sweep accumulator to the conventional sigma-delta fractional-N divider to produce a N.F value that is a polynomial function of time. This allows any non-linear sweep profiles to be approximated.

Abstract: This invention adds a non-linear sweep accumulator to the conventional sigma-delta fractional-N divider to produce a N.F value that is a polynomial function of time. This allows any non-linear sweep profiles to be approximated.

Abstract: An adaptive cycle-slipped detector (“ACSD”) for use in a Phase-Locked Loop (“PLL”) circuit. The ACSD may include a phase comparator, a phase shifter in signal communication with the phase comparator, and a cycle-slipped detector (“CSD”) in signal communication with the phase shifter.

Abstract: A signal synthesizer includes a high frequency offset stage having a high frequency offset source and frequency translation element in the feedback path of a dual-oscillator offset loop synthesizer. The signal synthesizer achieves low phase noise via noise cancellation when used to provide the first local oscillator of a spectrum analyzer and when the second local oscillator of the spectrum analyzer provides the high frequency offset source to the signal synthesizer.

Abstract: A direct frequency synthesizer provides an output signal derived from a high frequency reference signal that is frequency divided and mixed to satisfy the coarse step synthesis requirements of an offset loop synthesizer. The absence of a VCO within the direct frequency synthesizer, provides the direct frequency synthesizer with lower phase noise than a typical PLL-based coarse step synthesizer. Though applicable to a variety of types of synthesizers and signal generators, the direct frequency synthesizer provides especially advantageous noise performance when used to generate an offset signal for an offset loop synthesizer of the first local oscillator of a spectrum analyzer, where the second local oscillator of the spectrum analyzer provides the reference signal for the direct frequency synthesizer.

Abstract: A microwave synthesizer apparatus features very low phase noise, fine frequency resolution and wide tuning range coverage. The microwave synthesizer apparatus utilizes a fundamental offset source in an offset phase lock loop (PLL) to translate an output signal Fout to a lower IF signal Fif for locking to a low frequency interpolation signal Fint. The use of the fundamental offset source instead of the conventional multiple frequency offset signal from a comb generator or sampler results in superior phase noise and spurious performance. The synthesizer comprises a main signal loop having a main loop VCO that produces an output signal Fout and an offset signal loop having an offset VCO that produces an output signal Fos. The signals Fos and Fout are mixed in the main loop to control the frequency of the signal Fout. The main loop VCO and the offset loop VCO preferably are YIG-tuned Oscillators (YTOs) that share a main coil.

Abstract: The device and method of the present invention characterizes a telephone call by identifying a code, comparing the code to a predetermined access/ID code and generating a signal in response to the code. The device provides called party identification, calling party identification, and telephone number identification.