Patents by Inventor Winston K. Chan

Winston K. Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240055545
    Abstract: An example image intensifier includes a quantum well infrared photodetector (QWIP) configured to receive photons to photoexcite carriers out of a localized quantum state; and a light emitting diode (LED), wherein the photoexcited carriers control the LED.
    Type: Application
    Filed: August 9, 2023
    Publication date: February 15, 2024
    Inventors: David John Hill, Winston K. Chan
  • Patent number: 11735692
    Abstract: Methods, systems, and apparatuses are described for a CMOS compatible substrate having multiple stacks of semiconductor layers. The multiple stacks, at least, each include i) a layer of a tellurium based semiconductor layer on top of ii) a porous silicon layer. The porous silicon layer is a compliant layer to accept structural defects from the tellurium based semiconductor layer into the porous silicon layer. The multiple stacks are grown on the CMOS compatible substrate.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 22, 2023
    Assignee: SRI International
    Inventor: Winston K. Chan
  • Patent number: 11688638
    Abstract: A system to manufacture a plurality of dies may include an etching tool, an electrically-conductive-adhesive-composition, a heat-applying-extraction-tool and a porous substrate cooperating with an evacuation component. The etching tool uses an ion beam that is configured to singulate a plurality of dies on a wafer with an ion etching process. The electrically-conductive-adhesive-composition is located between the wafer and a porous substrate carrying the wafer during the ion etching process. The electrically-conductive-adhesive-composition adheres the wafer to the porous substrate to keep the dies in place during the ion etching process. The electrically-conductive-adhesive-composition also aids in conducting electrons away from the wafer as a drain during the ion etching process.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: June 27, 2023
    Assignee: SRI International
    Inventors: Winston K. Chan, Joey J. Michalchuk
  • Patent number: 11580344
    Abstract: An integrated circuit having Radio Frequency Identification components and circuitry used for authentication is discussed. The RFID components and circuitry include two or more coils and corresponding electrical circuits that are tuned to use two or more different resonant frequencies including: a first resonant RF used for power generation and a second resonant RF used for data communication. The integrated circuit contains a unique signature that is used for the authentication with two or more aspects including i) a first aspect that is a programmed password in a memory embedded on the integrated circuit, and ii) a second aspect that is a unique, randomly generated code based upon a physical characteristic of the integrated circuit.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: February 14, 2023
    Assignee: SRI International
    Inventors: Sterling E. McBride, Michael G. Kane, Alex Krasner, Richard Sita, Winston K. Chan, Mark F. Schutzer
  • Patent number: 11569077
    Abstract: The disclosure includes an outer electrode and an inner electrode. The outer electrode defines an inner volume and is configured to receive injected electrons through at least one aperture. The inner electrode positioned in the inner volume. The outer electrode and inner electrode are configured to confine the received electrons in orbits around the inner electrode in response to an electric potential between the outer electrode and the inner electrode. The apparatus does not include a component configured to generate an electron-confining magnetic field.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: January 31, 2023
    Assignee: SRI INTERNATIONAL
    Inventors: Sterling Eduardo McBride, Joey J. Michalchuk, Christopher E. Holland, Ashish Chaudhary, Winston K. Chan
  • Publication number: 20220209040
    Abstract: A photodiode, such as a linear mode avalanche photodiode can be made free of excess noise via having a superlattice multiplication region that allows only one electrical current carrier type, such as an electron or a hole, to accumulate enough kinetic energy to impact ionize when biased, where the layers are lattice matched. A photodiode can be constructed with i) a lattice matched pair of a first semiconductor alloy and a second semiconductor alloy in a superlattice multiplication region, ii) an absorber region, and iii) a semiconductor substrate. A detector with multiple photodiodes can be made with these construction layers in order to have a cutoff wavelength varied anywhere from 1.7 to 4.9 ?m as well as a noise resulting from a dark current at a level such that an electromagnetic radiation signal with the desired minimum wavelength cutoff can be accurately sensed by the photodiode.
    Type: Application
    Filed: January 19, 2022
    Publication date: June 30, 2022
    Inventor: Winston K. Chan
  • Patent number: 11362232
    Abstract: A photodiode, such as a linear mode avalanche photodiode can be made free of excess noise via having a superlattice multiplication region that allows only one electrical current carrier type, such as an electron or a hole, to accumulate enough kinetic energy to impact ionize when biased, where the layers are lattice matched. A photodiode can be constructed with i) a lattice matched pair of a first semiconductor alloy and a second semiconductor alloy in a superlattice multiplication region, ii) an absorber region, and iii) a semiconductor substrate. A detector with multiple photodiodes can be made with these construction layers in order to have a cutoff wavelength varied anywhere from 1.7 to 4.9 ?m as well as a noise resulting from a dark current at a level such that an electromagnetic radiation signal with the desired minimum wavelength cutoff can be accurately sensed by the photodiode.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: June 14, 2022
    Assignee: SRI International
    Inventor: Winston K. Chan
  • Patent number: 11271130
    Abstract: A linear mode avalanche photodiode senses light and outputs electrical current by being configured to, generate a gain equal to or greater than 1000 times amplification while generating an excess noise factor of less than 3 times a thermal noise present at or above a non-cryogenic temperature due to the gain from the amplification. The linear mode avalanche photodiode detects one or more photons in the light by using a superlattice structure that is matched to suppress impact ionization for a first carrier in the linear mode avalanche photodiode while at least one of 1) increasing impact ionization, 2) substantially maintaining impact ionization, and 3) suppressing impact ionization to a lesser degree for a second carrier. The first carrier having its impact ionization suppressed is either i) an electron or ii) a hole; and then, the second carrier is the electron or the hole.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: March 8, 2022
    Assignee: SRI International
    Inventor: Winston K. Chan
  • Publication number: 20210359160
    Abstract: Methods, systems, and apparatuses are described for a CMOS compatible substrate having multiple stacks of semiconductor layers. The multiple stacks, at least, each include i) a layer of a tellurium based semiconductor layer on top of ii) a porous silicon layer. The porous silicon layer is a compliant layer to accept structural defects from the tellurium based semiconductor layer into the porous silicon layer. The multiple stacks are grown on the CMOS compatible substrate.
    Type: Application
    Filed: August 22, 2019
    Publication date: November 18, 2021
    Inventor: Winston K. Chan
  • Publication number: 20210249552
    Abstract: A photodiode, such as a linear mode avalanche photodiode can be made free of excess noise via having a superlattice multiplication region that allows only one electrical current carrier type, such as an electron or a hole, to accumulate enough kinetic energy to impact ionize when biased, where the layers are lattice matched. A photodiode can be constructed with i) a lattice matched pair of a first semiconductor alloy and a second semiconductor alloy in a superlattice multiplication region, ii) an absorber region, and iii) a semiconductor substrate. A detector with multiple photodiodes can be made with these construction layers in order to have a cutoff wavelength varied anywhere from 1.7 to 4.9 ?m as well as a noise resulting from a dark current at a level such that an electromagnetic radiation signal with the desired minimum wavelength cutoff can be accurately sensed by the photodiode.
    Type: Application
    Filed: May 24, 2019
    Publication date: August 12, 2021
    Inventor: Winston K. CHAN
  • Publication number: 20210217918
    Abstract: A linear mode avalanche photodiode senses light and outputs electrical current by being configured to, generate a gain equal to or greater than 1000 times amplification while generating an excess noise factor of less than 3 times a thermal noise present at or above a non-cryogenic temperature due to the gain from the amplification. The linear mode avalanche photodiode detects one or more photons in the light by using a superlattice structure that is matched to suppress impact ionization for a first carrier in the linear mode avalanche photodiode while at least one of 1) increasing impact ionization, 2) substantially maintaining impact ionization, and 3) suppressing impact ionization to a lesser degree for a second carrier. The first carrier having its impact ionization suppressed is either i) an electron or ii) a hole; and then, the second carrier is the electron or the hole.
    Type: Application
    Filed: July 11, 2018
    Publication date: July 15, 2021
    Inventor: Winston K. Chan
  • Publication number: 20210158121
    Abstract: An integrated circuit having Radio Frequency Identification components and circuitry used for authentication is discussed. The RFID components and circuitry include two or more coils and corresponding electrical circuits that are tuned to use two or more different resonant frequencies including: a first resonant RF used for power generation and a second resonant RF used for data communication. The integrated circuit contains a unique signature that is used for the authentication with two or more aspects including i) a first aspect that is a programmed password in a memory embedded on the integrated circuit, and ii) a second aspect that is a unique, randomly generated code based upon a physical characteristic of the integrated circuit.
    Type: Application
    Filed: March 27, 2018
    Publication date: May 27, 2021
    Inventors: Sterling E. McBride, Michael G. Kane, Alex Krasner, Richard Sita, Winston K. Chan, Mark F. Schutzer
  • Publication number: 20210125867
    Abstract: A system to manufacture a plurality of dies may include an etching tool, an electrically-conductive-adhesive-composition, a heat-applying-extraction-tool and a porous substrate cooperating with an evacuation component. The etching tool uses an ion beam that is configured to singulate a plurality of dies on a wafer with an ion etching process. The electrically-conductive-adhesive-composition is located between the wafer and a porous substrate carrying the wafer during the ion etching process. The electrically-conductive-adhesive-composition adheres the wafer to the porous substrate to keep the dies in place during the ion etching process. The electrically-conductive-adhesive-composition also aids in conducting electrons away from the wafer as a drain during the ion etching process.
    Type: Application
    Filed: March 27, 2018
    Publication date: April 29, 2021
    Inventors: Winston K. Chan, Joey J. Michalchuk
  • Publication number: 20200343081
    Abstract: The disclosure includes an outer electrode and an inner electrode. The outer electrode defines an inner volume and is configured to receive injected electrons through at least one aperture. The inner electrode positioned in the inner volume. The outer electrode and inner electrode are configured to confine the received electrons in orbits around the inner electrode in response to an electric potential between the outer electrode and the inner electrode. The apparatus does not include a component configured to generate an electron-confining magnetic field.
    Type: Application
    Filed: July 11, 2018
    Publication date: October 29, 2020
    Inventors: Sterling Eduardo McBride, Joey J. Michalchuk, Christopher E. Holland, Ashish Chaudhary, Winston K. Chan
  • Patent number: 10541090
    Abstract: The invention pertains to the field of electronic devices and the preparation thereof. In an aspect is an electronic device comprising a nanocomposite of carbon nanodomains homogeneously embedded in an insulating ceramic matrix, wherein the size and distribution of carbon nanodomains is such that the nanocomposite has a permittivity of greater than or equal to 200.
    Type: Grant
    Filed: September 6, 2015
    Date of Patent: January 21, 2020
    Assignee: SRI International
    Inventors: Yigal D Blum, Winston K. Chan, John W. Hodges, David K. Hui, Srinivasan Krishnamurthy, David Brent McQueen, Marc Rippen
  • Publication number: 20160005552
    Abstract: The invention pertains to the field of electronic devices and the preparation thereof. In an aspect is an electronic device comprising a nanocomposite of carbon nanodomains homogeneously embedded in an insulating ceramic matrix, wherein the size and distribution of carbon nanodomains is such that the nanocomposite has a permittivity of greater than or equal to 200.
    Type: Application
    Filed: September 6, 2015
    Publication date: January 7, 2016
    Applicant: SRI INTERNATIONAL
    Inventors: Yigal D. Blum, Winston K. Chan, John W. Hodges, David K. Hui, Srinivasan Krishnamurthy, David Brent McQueen, Marc Rippen
  • Patent number: 7082249
    Abstract: An optical system including: a substrate having a recess; and, a substantially planar, semiconductor waveguiding membrane suspended over the recess and having a thickness less than about 200 nm; wherein, the optical system supports a propagating optical mode having a majority of its energy external to the semiconductor waveguiding membrane.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: July 25, 2006
    Assignee: Sarnoff Corporation
    Inventors: Ralph D. Whaley, Jr., Joseph H. Abeles, Martin H. Kwakernaak, Viktor B. Khalfin, Winston K. Chan, Haiyan An, Steven Lipp
  • Patent number: 6636666
    Abstract: The methods and apparatus according to the invention equalize the power of at least one frequency in a multi-wavelength optical signal, or limit the power contained in a single or multi-frequency signal. More particularly, the optical power equalizer according to the invention is a filter with separably variable wavelength dependent transmission coefficients, wherein each coefficient decreases with increasing power for each respective wavelength coupled to the equalizer. Thus, the highest power wavelength output from an EDFA will be filtered more than the lower power wavelengths, making the output power from the EDFA more evenly distributed among the wavelengths. Such an equalizer can be placed downstream from each EDFA without destabilizing the optical network so that no changes need to be made to the EDFA or to the other components in the system.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: October 21, 2003
    Assignee: University of Iowa Research Foundation
    Inventors: Winston K. Chan, David R. Andersen
  • Patent number: 6624510
    Abstract: An electrode array includes a flexible substrate, and a plurality of electrodes disposed on the flexible substrate. The flexible substrate is preferably formed of polyimide. The contacts preferably have a diameter in the range of approximately 10 &mgr;m to 1 mm. The an electrode array is manufactured by forming a plurality of electrodes on a flexible substrate by forming a metal line on the flexible substrate for each of the plurality of electrodes by depositing one or more metals using electron beam evaporation and then patterning the one or more metals and forming a contact on the flexible substrate for each of the plurality of electrodes using one of electroplating and embossing, and then forming an insulating film on the flexible substrate except over the contacts and areas of the electrodes utilized for connections to an electrical device.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: September 23, 2003
    Assignee: University of Iowa Research Foundation
    Inventors: Winston K. Chan, Chris Coretsopoulos, Matthew A. Howard, III
  • Publication number: 20020181867
    Abstract: The methods and apparatus according to the invention equalize the power of at least one frequency in a multi-wavelength optical signal, or limit the power contained in a single or multi-frequency signal. More particularly, the optical power equalizer according to the invention is a filter with separably variable wavelength dependent transmission coefficients, wherein each coefficient decreases with increasing power for each respective wavelength coupled to the equalizer. Thus, the highest power wavelength output from an EDFA will be filtered more than the lower power wavelengths, making the output power from the EDFA more evenly distributed among the wavelengths. Such an equalizer can be placed downstream from each EDFA without destabilizing the optical network so that no changes need to be made to the EDFA or to the other components in the system.
    Type: Application
    Filed: May 14, 2001
    Publication date: December 5, 2002
    Inventors: Winston K. Chan, David R. Andersen