Abstract: A one-time programmable (OTP) memory device includes a memory array having multiple memory elements. The memory array includes a plurality of anti-fuse FinFETs and a plurality of access FinFETs. Each anti-fuse device has a first terminal for receiving a programming voltage and a second terminal. The anti-fuse FinFETs are located in a first region of an integrated circuit. At least one anti-fuse FinFET of the plurality of anti-fuse FinFETs and at least one access FinFET of the plurality of access FinFETs form a memory element of the plurality of memory elements of the memory array. Each access FinFET is configured to selectively couple one of a program inhibit voltage and a program enable voltage to the second terminal of a corresponding anti-fuse FinFET in a programming operation. The access FinFETs are located in a second region of the integrated circuit, different than the first region of the integrated circuit.

Abstract: A one-time programmable (OTP) memory device includes a memory array having multiple memory elements. The memory array includes a plurality of anti-fuse FinFETs and a plurality of access FinFETs. Each anti-fuse device has a first terminal for receiving a programming voltage and a second terminal. The anti-fuse FinFETs are located in a first region of an integrated circuit. At least one anti-fuse FinFET of the plurality of anti-fuse FinFETs and at least one access FinFET of the plurality of access FinFETs form a memory element of the plurality of memory elements of the memory array. Each access FinFET is configured to selectively couple one of a program inhibit voltage and a program enable voltage to the second terminal of a corresponding anti-fuse FinFET in a programming operation. The access FinFETs are located in a second region of the integrated circuit, different than the first region of the integrated circuit.

Abstract: A method and system for suppressing power signature in a memory device during read operations. A memory array stores data in an even number of cells per bit, such as 2 cells per bit, where complementary data states are stored in each pair of cells. Differential read out of the memory array via the bitlines suppresses power signature because the same power consumption occurs regardless of the data being accessed from the memory array. Data output buffers that provide complementary data to a downstream circuit system are reset to the same logic state prior to every read operation such that only one output buffer (in the complementary output buffer pair) is ever driven to the opposite logic state in each read cycle. Hence the power consumption remains the same regardless of the data states being read out from the memory array and provided by the output buffers.

Abstract: A method and system for suppressing power signature in a memory device during read operations. A memory array stores data in an even number of cells per bit, such as 2 cells per bit, where complementary data states are stored in each pair of cells. Differential read out of the memory array via the bitlines suppresses power signature because the same power consumption occurs regardless of the data being accessed from the memory array. Data output buffers that provide complementary data to a downstream circuit system are reset to the same logic state prior to every read operation such that only one output buffer (in the complementary output buffer pair) is ever driven to the opposite logic state in each read cycle. Hence the power consumption remains the same regardless of the data states being read out from the memory array and provided by the output buffers.

Abstract: A one time programmable memory cell having twin wells to improve dielectric breakdown while minimizing current leakage. The memory cell is manufactured using a standard CMOS process used for core and I/O (input/output) circuitry. A two transistor memory cell having an access transistor and an anti-fuse device, or a single transistor memory cell 100 having a dual thickness gate oxide 114 & 116, are formed in twin wells 102 & 104. The twin wells are opposite in type to each other, where one can be an N-type well 102 while the other can be a P-type well 104. The anti-fuse device is formed with a thin gate oxide and in a well similar to that used for the core circuitry. The access transistor is formed with a thick gate oxide and in a well similar to that used for I/O circuitry.

Abstract: An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide is formed by depositing a first oxide over a channel region of the anti-fuse memory cell, removing the first oxide in a thin oxide area of the channel region, and then thermally growing a second oxide in the thin oxide area. The remaining first oxide defines a thick oxide area of the channel region. The second oxide growth occurs under the remaining first oxide, but at a rate less than thermal oxide growth in the thin oxide area. This results in a combined thickness of the first oxide and the second oxide in the thick oxide area being greater than second oxide in the thin oxide area.

Abstract: A redundancy scheme for Non-Volatile Memories (NVM) is described. This redundancy scheme provides means for using defective cells in non-volatile memories to increase yield. The algorithm is based on inverting the program data for data being programmed to a cell grouping when a defective cell is detected in the cell grouping. Defective cells are biased to either “1” or “0” logic states, which are effectively preset to store its biased logic state. A data bit to be stored in a defective cell having a logic state that is complementary to the biased logic state of the cell results in the program data being inverted and programmed. An inversion status bit is programmed to indicate the inverted status of the programmed data. During read out, the inversion status bit causes the stored data to be re-inverted into its original program data states.

Abstract: A one time programmable memory cell having an anti-fuse device with a low threshold voltage independent of core circuit process manufacturing technology is presented. A two transistor memory cell having a pass transistor and an anti-fuse device, or a single transistor memory cell having a dual thickness gate oxide, are formed in a high voltage well that is formed for high voltage transistors. The threshold voltage of the anti-fuse device differs from the threshold voltages of any transistor in the core circuits of the memory device, but has a gate oxide thickness that is the same as a transistor in the core circuits. The pass transistor has a threshold voltage that differs from the threshold voltages of any transistor in the core circuits, and has a gate oxide thickness that differs from any transistor in the core circuits.

Abstract: An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide is formed by depositing a first oxide over a channel region of the anti-fuse memory cell, removing the first oxide in a thin oxide area of the channel region, and then thermally growing a second oxide in the thin oxide area. The remaining first oxide defines a thick oxide area of the channel region. The second oxide growth occurs under the remaining first oxide, but at a rate less than thermal oxide growth in the thin oxide area. This results in a combined thickness of the first oxide and the second oxide in the thick oxide area being greater than second oxide in the thin oxide area.

Abstract: Methods for testing unprogrammed single transistor and two transistor anti-fuse memory cells include testing for connections of the cells to a bitline by comparing a voltage characteristic of a bitline connected to the cell under test to a reference bitline having a predetermined voltage characteristic. Some methods can use test cells having an access transistor identically configured to the access transistor of a normal memory cell, but omitting the anti-fuse device found in the normal memory cell, for testing the presence of a connection of the normal memory cell to the bitline. Such a test cell can be used in a further test for determining the level of capacitive coupling of the wordline voltage to the bitlines relative to that of a normal memory cell under test.

Abstract: A redundancy scheme for Non-Volatile Memories (NVM) is described. This redundancy scheme provides means for using defective cells in non-volatile memories to increase yield. The algorithm is based on inverting the program data for data being programmed to a cell grouping when a defective cell is detected in the cell grouping. Defective cells are biased to either “1” or “0” logic states, which are effectively preset to store its biased logic state. A data bit to be stored in a defective cell having a logic state that is complementary to the biased logic state of the cell results in the program data being inverted and programmed. An inversion status bit is programmed to indicate the inverted status of the programmed data. During read out, the inversion status bit causes the stored data to be re-inverted into its original program data states.

Abstract: A method for fabricating an anti-fuse memory cell having a semiconductor structure with a minimized area. The method includes providing a reference pattern for the semiconductor structure, and applying a reverse OPC technique that includes inverting selected corners of the reference pattern. The reverse OPC technique uses photolithographic distortions to provide a resulting fabricated pattern that is intentionally distorted relative to the reference pattern. By inverting corners of a geometric reference pattern, the resulting distorted pattern will have an area that is reduced relative to the original reference pattern. This technique is advantageous for reducing the area of a selected region of a semiconductor structure which may otherwise not be possible through normal design parameters.

Abstract: A redundancy scheme for Non-Volatile Memories (NVM) is described. This redundancy scheme provides means for using defective cells in non-volatile memories to increase yield. The algorithm is based on inverting the program data for data being programmed to a cell grouping when a defective cell is detected in the cell grouping. Defective cells are biased to either “1” or “0” logic states, which are effectively preset to store its biased logic state. A data bit to be stored in a defective cell having a logic state that is complementary to the biased logic state of the cell results in the program data being inverted and programmed. An inversion status bit is programmed to indicate the inverted status of the programmed data. During read out, the inversion status bit causes the stored data to be re-inverted into its original program data states.

Abstract: Test cells are included in a one-time programmable (OTP) memory array for detecting semiconductor fabrication misalignment, which can result in a potentially defective memory array. The test cells are fabricated at the same time as the normal OTP cells, except they are smaller in size along one dimension in order to detect mask misalignment along that dimension. Any fabricated test cell which cannot be programmed indicates a level of fabrication mask misalignment has occurred and the OTP memory array should not be used.

Abstract: An AND-type anti-fuse memory cell, and a memory array consisting of AND-type anti-fuse memory cells. Chains of AND type anti-fuse cells are connected in series with each other, and with a bitline contact, in order to minimize the area occupied by the memory array. Each AND type anti-fuse cell includes an access transistor serially connectable to the bitline or the access transistors of other AND type anti-fuse cells, and an anti-fuse device. The channel region of the access transistor is connected to the channel region of the anti-fuse device, and both channel regions are covered by the same wordline. The wordline is driven to a programming voltage level for programming the anti-fuse device, or to a read voltage level for reading the anti-fuse device.

Abstract: A redundancy scheme for Non-Volatile Memories (NVM) is described. This redundancy scheme provides means for using defective cells in non-volatile memories to increase yield. The algorithm is based on inverting the program data for data being programmed to a cell grouping when a defective cell is detected in the cell grouping. Defective cells are biased to either “1” or “0” logic states, which are effectively preset to store its biased logic state. A data bit to be stored in a defective cell having a logic state that is complementary to the biased logic state of the cell results in the program data being inverted and programmed. An inversion status bit is programmed to indicate the inverted status of the programmed data. During read out, the inversion status bit causes the stored data to be re-inverted into its original program data states.

Abstract: An anti-fuse memory cell having a variable thickness gate dielectric. The variable thickness dielectric has a thick portion and a thin portion, where the thin portion has at least one dimension less than a minimum feature size of a process technology. The thin portion can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate dielectric substantially identical in thickness to the thick portion of the variable thickness gate dielectric of the anti-fuse transistor.

Abstract: Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor.

Abstract: A method for operating a register stage of a dual function data register. A data register having master and slave latching circuits is used for concurrently storing two different words of data. Data is shifted into the master latching circuit in response to a first clock signal, and data stored in the master latching circuit is shifted into the slave latching circuit in response to a second clock signal. The first and second clocks are generated from a source clock in response to a control signal, which can be asserted at different times to initiate shifting operations from either the master latching circuit or the slave latching circuit. In otherwords, shifting operations can be initiated either on a rising edge of the source clock, or on a falling edge of the source clock.

Abstract: A one time programmable memory cell having twin wells to improve dielectric breakdown while minimizing current leakage. The memory cell is manufactured using a standard CMOS process used for core and I/O (input/output) circuitry. A two transistor memory cell having an access transistor and an anti-fuse device, or a single transistor memory cell 100 having a dual thickness gate oxide 114 & 116, are formed in twin wells 102 & 104. The twin wells are opposite in type to each other, where one can be an N-type well 102 while the other can be a P-type well 104. The anti-fuse device is formed with a thin gate oxide and in a well similar to that used for the core circuitry. The access transistor is formed with a thick gate oxide and in a well similar to that used for I/O circuitry.