Abstract: To increase the efficiency of electronic design automation, a register transfer level debug application client entity requests, from a register transfer level source navigator server, combined register transfer level and hardware aspect metadata including debug instrumentation. The register transfer level debug application client entity receives, from the register transfer level source navigator server, the combined register transfer level and hardware aspect metadata including the debug instrumentation. The register transfer level debug application client entity transforms the combined register transfer level and hardware aspect metadata including the debug instrumentation. The register transfer level debug application client entity renders the transformed combined register transfer level and hardware aspect metadata including the debug instrumentation.

Abstract: A method, computer program product, and/or system is disclosed for testing integrated circuits, e.g., processors, that includes: generating a software design prototype of the functional behavior of an integrated circuit to be tested; creating a lab All-Events-Trace (AET) normalized model of the integrated circuit, wherein the normalized model captures the functions of the integrated circuit and not the non-functional aspects of the integrated circuit; generating a lab scenario using the software design prototype and the AET normalized model of the integrated circuit for a particular cycle of interest, wherein the lab scenario contains initialization for all signals that have hardware information; and generating a replayed lab normalized AET for the particular cycle of interest.

Abstract: A method, programming product, and/or system is disclosed for identifying flaws in integrated circuits, e.g., processors, that includes: selecting from a list of a plurality of timing issues in an integrated circuit, where each timing issue on the list is represented by one or more VHDL code lines, a particular timing issue to investigate; tracing back the selected one or more VHDL code lines, corresponding to the selected particular timing issue to investigate, to one or more selected physical design VHDL (PD-VHDL) code lines; logically navigating across the one or more selected PD-VHDL code lines to one or more corresponding normalized VHDL (NVDHL) code lines; and tracing back the one or more corresponding NHVDL code lines to one or more short-hand VHDL (SVHDL) code lines to identify one or more code lines, written by a code designer, responsible for the particular timing issue being investigated.

Abstract: A processor receives, as input, a first hardware description language (HDL) file defining an entity of a modular circuit design. The first HDL file instantiates, by a storage element declaration in a hardware description language, a storage element within the entity. The first HDL file omits a port map for the storage element. Based on the first HDL file, the processor automatically fully elaborates a port map for the storage element. The processor stores, in data storage, a derived second HDL file defining the entity and including the port map.

Abstract: A method for collaborative logic designing and debugging of a circuit includes initiating, via a session manager, a hardware debug session that includes a plurality of instances of client applications that can access one or more source-codes associated with a logic design of the circuit, the plurality of instances of client applications configured to replicate an execution state of the logic design. The method also includes analyzing, using an instance of a first client application from the plurality of instances of client applications, a defect in the logic design based on the execution state of the logic design. The method also includes editing, using an instance of a second client application from the plurality of instances of client applications, the one or more source-codes, to repair the defect in the logic design.

Abstract: To increase the efficiency of electronic design automation, a register transfer level debug application client entity requests, from a register transfer level source navigator server, combined register transfer level and hardware aspect metadata including debug instrumentation. The register transfer level debug application client entity receives, from the register transfer level source navigator server, the combined register transfer level and hardware aspect metadata including the debug instrumentation. The register transfer level debug application client entity transforms the combined register transfer level and hardware aspect metadata including the debug instrumentation. The register transfer level debug application client entity renders the transformed combined register transfer level and hardware aspect metadata including the debug instrumentation.

Abstract: A method, computer program product, and/or system is disclosed for testing integrated circuits, e.g., processors, that includes: generating a software design prototype of the functional behavior of an integrated circuit to be tested; creating a lab All-Events-Trace (AET) normalized model of the integrated circuit, wherein the normalized model captures the functions of the integrated circuit and not the non-functional aspects of the integrated circuit; generating a lab scenario using the software design prototype and the AET normalized model of the integrated circuit for a particular cycle of interest, wherein the lab scenario contains initialization for all signals that have hardware information; and generating a replayed lab normalized AET for the particular cycle of interest.

Abstract: A first plurality of hardware description language (HDL) files describe a hierarchical integrated circuit design utilizing a simplified HDL syntax that omits specification of logical clock connections for at least some entities in the hierarchical integrated circuit design. The hierarchical integrated circuit design as described by the first plurality of HDL files is processed to automatically add logical clock connections for entities in the hierarchical integrated circuit design for which specification of logical clock connections are omitted in the first plurality of HDL files. Based on the processing, a second plurality of HDL files defining the hierarchical integrated circuit design is generated.

Abstract: A processor receives an expression of design refinement intent with regard to an entity forming a part of a modular circuit design. The entity is defined by a hardware description language (HDL) file, and the expression of design refinement intent identifies an intent region within an implementation of the entity and specifies replacement logic for the region. Based on the expression of design refinement intent, the processor automatically modifies the HDL file by replacing logic within the intent region with the replacement logic. The processor then performs logical synthesis to generate a gate list representation of the modular circuit design as modified.

Abstract: A processor receives, as input, a first hardware description language (HDL) file defining an entity of a modular circuit design. The first HDL file instantiates, by a storage element declaration in a hardware description language, a storage element within the entity. The first HDL file omits a port map for the storage element. Based on the first HDL file, the processor automatically fully elaborates a port map for the storage element. The processor stores, in data storage, a derived second HDL file defining the entity and including the port map.

Abstract: A first plurality of hardware description language (HDL) files defines a first scope of design forming only a subset of a larger hierarchical integrated circuit design. Technology-specific structures specific to a physical implementation are incorporated in the first scope of design. A second plurality of HDL files defining a first design entity that is at the first scope of design and that includes the technology-specific structures is generated. A third plurality of HDL files defining a second scope of design for the hierarchical integrated circuit design that is larger than and includes the first scope of design is formed. The third plurality of HDL files is processed to form a representation of the second scope of design. Processing the third plurality of HDL files includes replacing a second design entity in the second scope of design lacking at least some technology-specific structures with the first design entity.

Abstract: Based on a directive in a control file, a processor pre-routes, within a hierarchical integrated circuit design, a signal through one or more levels of design hierarchy between a signal source at a higher level of the design hierarchy and an entity instance at a lower level of the design hierarchy. The processor processes entity instances in the design hierarchy in a bottom-up manner to insert technology-specific structures into the hierarchical integrated circuit design. During the processing, the processor inserts into a particular entity instance of the design hierarchy a technology-specific structure and connects the technology-specific structure to the signal pre-routed to the particular entity instance by the pre-routing.

Abstract: A semiconductor device includes an IGBT in an IGBT portion of a semiconductor body and a diode in a diode portion of the semiconductor body. The diode includes an anode region of a first conductivity type and confined by diode trenches along a first lateral direction. Each of the diode trenches includes a diode trench electrode and a diode trench dielectric. A first contact groove extends into the anode region along a vertical direction from the first surface of the semiconductor body. An anode contact region of the first conductivity type adjoins a bottom side of the first contact groove. A cathode contact region of a second conductivity type adjoins a second surface of the semiconductor body opposite to the first surface. The IGBT includes a gate trench including a gate electrode and a gate dielectric, a source region, an emitter electrode, a drift region, and a second contact groove.

Abstract: A semiconductor device is proposed. The semiconductor device includes an IGBT in an IGBT portion of a semiconductor body and a diode in a diode portion of the semiconductor body. The diode includes an anode region of a first conductivity type and confined by diode trenches along a first lateral direction. Each of the diode trenches includes a diode trench electrode and a diode trench dielectric. A first contact groove extends into the anode region along a vertical direction from the first surface of the semiconductor body. An anode contact region of the first conductivity type adjoins a bottom side of the first contact groove. A cathode contact region of a second conductivity type adjoins a second surface of the semiconductor body opposite to the first surface. Methods of manufacturing the semiconductor device are also proposed.

Abstract: According to an embodiment of a power semiconductor device, the device includes: a semiconductor substrate including an IGBT region having an IGBT and a diode region having a diode. The IGBT region includes a plurality of first trenches extending perpendicular to a first main surface of the semiconductor substrate. The diode region includes a plurality of second trenches extending perpendicular to the first main surface of the semiconductor substrate. An average lateral spacing between adjacent ones of the second trenches is greater than an average lateral spacing between adjacent ones of the first trenches. Additional power semiconductor device embodiments are described herein, as are corresponding methods of production.

Abstract: A method for collaborative logic designing and debugging of a circuit includes initiating, via a session manager, a hardware debug session that includes a plurality of instances of client applications that can access one or more source-codes associated with a logic design of the circuit, the plurality of instances of client applications configured to replicate an execution state of the logic design. The method also includes analyzing, using an instance of a first client application from the plurality of instances of client applications, a defect in the logic design based on the execution state of the logic design. The method also includes editing, using an instance of a second client application from the plurality of instances of client applications, the one or more source-codes, to repair the defect in the logic design.

Abstract: According to an embodiment of a power semiconductor device, the device includes: a semiconductor substrate including an IGBT region having an IGBT and a diode region having a diode. The IGBT region includes a plurality of first trenches extending perpendicular to a first main surface of the semiconductor substrate. The diode region includes a plurality of second trenches extending perpendicular to the first main surface of the semiconductor substrate. An average lateral spacing between adjacent ones of the second trenches is greater than an average lateral spacing between adjacent ones of the first trenches. Additional power semiconductor device embodiments are described herein, as are corresponding methods of production.

Abstract: A semiconductor device is proposed. The semiconductor device includes an IGBT in an IGBT portion of a semiconductor body and a diode in a diode portion of the semiconductor body. The diode includes an anode region of a first conductivity type and confined by diode trenches along a first lateral direction. Each of the diode trenches includes a diode trench electrode and a diode trench dielectric. A first contact groove extends into the anode region along a vertical direction from the first surface of the semiconductor body. An anode contact region of the first conductivity type adjoins a bottom side of the first contact groove. A cathode contact region of a second conductivity type adjoins a second surface of the semiconductor body opposite to the first surface. Methods of manufacturing the semiconductor device are also proposed.

Abstract: An embodiment relates to a method of manufacturing an insulated gate bipolar transistor in a semiconductor body. A first field stop zone portion of a first conductivity type is formed on a semiconductor substrate. A second field stop zone portion of the first conductivity type is formed on the first field stop zone portion. A drift zone of the first conductivity type is formed on the second field stop zone portion. A doping concentration in the drift zone is smaller than 1013 cm?3 along a vertical extension of more than 30% of a thickness of the semiconductor body upon completion of the insulated gate bipolar transistor.

Abstract: Method and apparatus for managing connections within a netlist include using a clone module to the connections between different components within the netlist. A buffer may be inserted between components of a netlist to split a connection into multiple segments and then moved into an associated first instance. The inclusion of the buffer allows for one or more of pin cloning and subway utilization to occur when mapping between a functional hierarchy to a physical hierarchy is performed.