Patents by Inventor Wolfgang Spirkl
Wolfgang Spirkl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10861533Abstract: Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line. The offset values are based on individual transition threshold voltages biases of sample circuits of the receiver circuit. The example apparatus may further include an input/output (I/O) circuit comprising a driver circuit. The driver circuit configured to receive a logic signal and the offset values and to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values.Type: GrantFiled: August 5, 2019Date of Patent: December 8, 2020Assignee: Micron Technology, Inc.Inventor: Wolfgang A. Spirkl
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Patent number: 10614904Abstract: Apparatuses and methods are provided for a high speed writing test mode for memories. An example apparatus includes a memory core, a data terminal coupled to a data receiver, a read buffer coupled between the data terminal and the memory core, and a write buffer coupled between the data receiver and the memory core. The write buffer may include at least a first input coupled to the data receiver, and a second input. While in a test mode, the write buffer may be loaded with data from the second input instead of the first input.Type: GrantFiled: October 18, 2018Date of Patent: April 7, 2020Assignee: Micron Technology, Inc.Inventors: Stefan Dietrich, Wolfgang Spirkl
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Publication number: 20190362773Abstract: Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line. The offset values are based on individual transition threshold voltages biases of sample circuits of the receiver circuit. The example apparatus may further include an input/output (I/O) circuit comprising a driver circuit. The driver circuit configured to receive a logic signal and the offset values and to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values.Type: ApplicationFiled: August 5, 2019Publication date: November 28, 2019Applicant: MICRON TECHNOLOGY, INC.Inventor: Wolfgang A. Spirkl
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Patent number: 10373674Abstract: Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line. The offset values are based on individual transition threshold voltages biases of sample circuits of the receiver circuit. The example apparatus may further include an input/output (I/O) circuit comprising a driver circuit. The driver circuit configured to receive a logic signal and the offset values and to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values.Type: GrantFiled: August 31, 2017Date of Patent: August 6, 2019Assignee: Micron Technology, Inc.Inventor: Wolfgang A. Spirkl
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Publication number: 20190066764Abstract: Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line. The offset values are based on individual transition threshold voltages biases of sample circuits of the receiver circuit. The example apparatus may further include an input/output (I/O) circuit comprising a driver circuit. The driver circuit configured to receive a logic signal and the offset values and to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values.Type: ApplicationFiled: August 31, 2017Publication date: February 28, 2019Applicant: MICRON TECHNOLOGY, INC.Inventor: Wolfgang A. Spirkl
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Publication number: 20190051369Abstract: Apparatuses and methods are provided for a high speed writing test mode for memories. An example apparatus includes a memory core, a data terminal coupled to a data receiver, a read buffer coupled between the data terminal and the memory core, and a write buffer coupled between the data receiver and the memory core. The write buffer may include at least a first input coupled to the data receiver, and a second input. While in a test mode, the write buffer may be loaded with data from the second input instead of the first input.Type: ApplicationFiled: October 18, 2018Publication date: February 14, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Stefan Dietrich, Wolfgang Spirkl
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Patent number: 10134482Abstract: Apparatuses and methods are provided for a high speed writing test mode for memories. An example apparatus includes a memory core, a data terminal coupled to a data receiver, a read buffer coupled between the data terminal and the memory core, and a write buffer coupled between the data receiver and the memory core. The write buffer may include at least a first input coupled to the data receiver, and a second input. While in a test mode, the write buffer may be loaded with data from the second input instead of the first input.Type: GrantFiled: January 17, 2017Date of Patent: November 20, 2018Assignee: Micron Technology, Inc.Inventors: Stefan Dietrich, Wolfgang Spirkl
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Publication number: 20180204630Abstract: Apparatuses and methods are provided for a high speed writing test mode for memories. An example apparatus includes a memory core, a data terminal coupled to a data receiver, a read buffer coupled between the data terminal and the memory core, and a write buffer coupled between the data receiver and the memory core. The write buffer may include at least a first input coupled to the data receiver, and a second input. While in a test mode, the write buffer may be loaded with data from the second input instead of the first input.Type: ApplicationFiled: January 17, 2017Publication date: July 19, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Stefan Dietrich, Wolfgang Spirkl
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Patent number: 8914589Abstract: Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access.Type: GrantFiled: September 22, 2008Date of Patent: December 16, 2014Assignee: Infineon Technologies AGInventors: Peter Gregorius, Thomas Hein, Martin Maier, Hermann Ruckerbauer, Thilo Schaffroth, Ralf Schedel, Wolfgang Spirkl, Johannes Stecker
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Patent number: 8635393Abstract: The invention relates to a method for reading data from a semiconductor memory, said method comprising the following steps in this order: providing at least one first memory bank and at least one shadow memory bank which are each designed to store a multiplicity of binary data items, the same data as in the first memory bank being stored in the shadow memory bank; receiving a command for reading data which are to be read from the first memory bank; utilizing a state checking device of the semiconductor memory to check whether the first memory bank is in an open memory bank state, and, if the first memory bank is in the open memory bank state, reading the data which are to be read from the at least one shadow memory bank, and, if the first memory bank is not in the open memory bank state, reading the data which are to be read from the first memory bank, the open memory state being such a memory state of the memory bank which does not allow the data which are to be read to be read without previously closing anType: GrantFiled: January 17, 2006Date of Patent: January 21, 2014Assignee: Qimonda AGInventors: Jean-Marc Dortu, Wolfgang Spirkl
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Patent number: 8495310Abstract: A system and method utilize a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated with a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, a plurality of memory devices may be arranged in a memory package in a stacked die memory configuration.Type: GrantFiled: September 22, 2008Date of Patent: July 23, 2013Assignee: Qimonda AGInventors: Peter Gregorius, Thomas Hein, Martin Maier, Hermann Ruckerbauer, Thilo Schaffroth, Ralf Schedel, Wolfgang Spirkl, Johannes Stecker
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Patent number: 7957254Abstract: A device for reducing mutual crosstalk of a signal routed across a first line and a second signal routed across a second line, wherein by the mutual crosstalk at an output of the first line a first interfered signal may be obtained and at an output of the second line a second interfered signal may be obtained, comprising a modifier for modifying the first interfered signal that is interfered by crosstalk due to the second signal, and for modifying the second interfered signal that is interfered by crosstalk due to the first signal, wherein the modifier is adapted to model an interference due to the mutual crosstalk, and a combiner for combining the first interfered signal with the modified second interfered signal to obtain a first corrected signal and for combining the second interfered signal with the modified first interfered signal to obtain a second corrected signal.Type: GrantFiled: March 18, 2008Date of Patent: June 7, 2011Assignee: Qimonda AGInventors: Wolfgang Spirkl, Holger Steffens
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Patent number: 7865795Abstract: Methods and apparatuses for generating a random sequence of commands for a semiconductor device. The method generates random state transitions within a finite state machine model of the semiconductor device. A sequence of commands is determined which are associated to the generated random state transitions based on the finite state machine model of the semiconductor device.Type: GrantFiled: February 28, 2008Date of Patent: January 4, 2011Assignee: Qimonda AGInventors: Thomas Nirmaier, Wolfgang Spirkl
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Patent number: 7757064Abstract: A method of sending data on request from a memory to a device, wherein the memory receives a request from the device for sending predetermined data to the device, wherein the memory sends data and information about the data to the device.Type: GrantFiled: September 7, 2006Date of Patent: July 13, 2010Assignee: Infineon Technologies AGInventors: Markus Balb, Peter Mayer, Wolfgang Spirkl, Christoph Bilger, Martin Brox, Thomas Hein, Michael Richter
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Patent number: 7757132Abstract: The invention relates to a memory with a memory array with memory cells, with an input/output circuit which is connected to the memory cells and which interchanges data with the memory cells, with an output register which is connected to the input/output circuit, with the output register being used to output data via a data output, having an input register which is connected to a data input and to the input/output circuit, with the data input and the input register being used to input data into the memory cells, with test data being written to the output register in a test mode. The invention furthermore relates to a process for testing a memory and to a memory module.Type: GrantFiled: May 23, 2007Date of Patent: July 13, 2010Assignee: Qimonda AGInventors: Wolfgang Spirkl, Martin Brox
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Patent number: 7746724Abstract: A method and apparatus for accessing a memory device. The method includes providing control signals for an access command to the memory device via an asynchronous interface and transmitting data for the access command to the memory device. The method also includes encoding, into the transmitted data, a clock signal. The encoded clock signal in the transmitted data is used by the memory device for receiving the data transmission.Type: GrantFiled: January 31, 2007Date of Patent: June 29, 2010Assignee: Qimonda AGInventors: Peter Mayer, Wolfgang Spirkl, Markus Balb, Christoph Bilger, Martin Brox, Thomas Hein, Michael Richter
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Patent number: 7728636Abstract: One aspect relates to a clock signal synchronizing device, in particular to a delayed locked loop (DLL) with capability to correct static duty-cycle offset and to filter clock-jitter. One aspect relates to a clock signal synchronizing method with capability to correct static duty-cycle offset and to filter clock-jitter. In accordance one aspect, there is provided a clock signal synchronizing device including a delay circuit having a variable delay time and delaying an incoming clock signal or a signal generated therefrom to output a delayed clock signal. Also included is a negator for inverting the delayed clock signal to output an inverted delayed clock signal. Also included is a delay control circuit for controlling the delay circuit to adjust the phase relation between the incoming clock signal and the inverted delayed clock signal and a phase interpolator.Type: GrantFiled: August 14, 2007Date of Patent: June 1, 2010Assignee: Qimonda AGInventors: Wolfgang Spirkl, Martin Brox, Holger Steffens
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Publication number: 20100077139Abstract: Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access.Type: ApplicationFiled: September 22, 2008Publication date: March 25, 2010Inventors: PETER GREGORIUS, THOMAS HEIN, MARTIN MAIER, HERMANN RUCKERBAUER, THILO SCHAFFROTH, RALF SCHEDEL, WOLFGANG SPIRKL, JOHANNES STECKER
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Publication number: 20100077157Abstract: Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, the memory device may be a package comprising a plurality of stacked memory dies.Type: ApplicationFiled: September 22, 2008Publication date: March 25, 2010Inventors: Peter Gregorius, Thomas Hein, Martin Maier, Hermann Ruckerbauer, Thilo Schaffroth, Ralf Schedel, Wolfgang Spirkl, Johannes Stecker
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Patent number: 7649130Abstract: An integrated circuit produced from non-monocrystalline semiconductors, including a plurality of transistors, all of the transistors being of the same type, and at least two timer signal inputs, wherein the timer signals fed to the different inputs are temporally non-overlapping signals.Type: GrantFiled: January 9, 2006Date of Patent: January 19, 2010Assignee: Infineon Technologies AGInventors: Wolfgang Spirkl, Gunter Schmid