Abstract: A single chip multiprocessing microprocessor having a synchronization register file is disclosed. This microprocessor includes a plurality of ILP (Instruction Level Parallelism) processors connecting through an internal bus, and a synchronization register file having a multiport so that the ILP processors concurrently access for thereby performing atomic instructions for thereby enhancing the performance of single chip multiprocessing microprocessor and a system using the same by processing atomic instruction without memory access when performing synchronization among internal processors.

Abstract: The present invention relates to a node connection apparatus. The 3-link node interconnection apparatus and parallel processing apparatus using the same confirm expanding nodes freely, only using fixed three connecting links, and are suitable to normal packaging method because of easy dividing into 2n (n>1) nodes. The apparatuses comprise the following nodes. The first node has three links connected to other nodes respectively. The second node has three links, one links of them is connected to the first node, and the other two links are in charge of connection of X+ direction, X− direction. The third node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Y+ direction, Y− direction. The fourth node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Z+ direction, Z− direction.

Abstract: An apparatus for controlling a cache in a computing node, which is located between a node bus and an interconnection network to perform a cache coherence protocol, includes: a node bus interface for interfacing with the node bus; an interconnection network interface for interfacing with the interconnection network; a cache control logic means for controlling the cache to perform the cache coherence protocol; bus-side dual-port transaction buffers coupled between said node bus interface and said cache control logic means for buffering transaction requested and replied from or to local processors contained in the computing node; and network-side dual-port transaction buffers coupled between said interconnection network interface and said cache control logic for buffering transaction requested and replied from or to remote processors contained in another computing node coupled to the interconnection network.

Abstract: The present invention relates to a routing control apparatus for performing a round robin arbitration and an adaptive routing control. The present invention relates to a routing controller for performing an arbitration and a routing control which are nucleus functions of the crossbar routing switch and, in particular, to a normal routing controller unit for performing a priority based round robin arbitration and an adaptive routing controller unit for performing an adaptive routing control by adding an adaptive routing switch logic to the normal routing controller.

Abstract: The present invention relates to a structure of processor having a plurality of main processors and sub processors, and a method for sharing the sub processors, wherein a method is used for preserving a state of a register file by using a shadow register file when main processor inputs an instruction of the sub processor in case that an exceptional situation happens under processing of an instruction of sub processor and for rolling back thereafter the preserved state in case there is an information of occurrence of the exceptional situation from the sub processor. Also, in order to solve a problem that cache efficiency is reduced due to the use of a first cache which is relatively small and frequently used, there is suggested a first cache bypassing function. Further, in order to solve a problem that its processing speed is reduced when the main processor transfers instructions in sub processor, it is possible to improve the processors' parallelism and its efficiency by providing an extra register file.

Abstract: A routing switch for constructing an interconnection network of a parallel processing computer is disclosed. A purpose of the present invention is to provide a crossbar routing switch for a hierarchical interconnection network which has an expandability of a data length and an expandability of a hierarchical structure. The crossbar routing switch for a hierarchical interconnection network in accordance with the present invention comprises a predetermined number of input control units for controlling one input port to perform the manipulation of input data; a crossbar core unit for analyzing a data transmission request by the input control unit and outputting the corresponding data; and a predetermined number of output control unit for controlling one output port and receiving the output data from the crossbar core unit to output it to the output port.

Abstract: The present invention relates to a hierarchical crossbar inter-connection network for a cluster-based parallel processing computer. A crossbar network is composed of the "n" number of crossbar switches which is byte sliced, eight links for connecting eight nodes, and two links for connecting other clusters. In addition, one low-level cluster is formed by connecting a maximum of eight processing nodes between the two crossbar networks, and one high-level cluster is formed with a maximum of eight low-level clusters and the four crossbar networks. Moreover, one next high-level clusters formed with a maximum of eight high-level clusters and the eight crossbar networks for scalability.

Abstract: A non-blocking fault tolerant gamma network for a multi-processor system is disclosed, including: N dual links respectively connected to n source nodes, and for transmitting data input; a first stage made up with n 2.times.3 switching devices for outputting data transmitted from the N dual links; a second stage made up with n 3.times.4 switching devices for outputting data output from the first stage; a third stage to n-1 stage made up with (n-2).times.N 4.times.4 switching devices for receiving data output from the second stage at the third stage and outputting the data to n-1 stage; an n stage made up with n 4.times.