Abstract: An image sensing device capable of minimizing reflection of light incident upon a metal layer is disclosed. The image sensing device includes a semiconductor substrate in which at least one groove is formed, a reflection prevention layer formed over the semiconductor substrate in a manner that the at least one groove is buried by the reflection prevention layer, and a metal layer formed over the reflection prevention layer, and provided with at least one through-hole corresponding to the at least one groove.

Abstract: An image sensing device includes an upper substrate configured to include a pixel region and a first peripheral region located outside the pixel region, a lower substrate configured to include a logic region and a second peripheral region located outside the logic region, the logic region configured to generate an image based on the electrical signals from the unit pixels, light reception elements disposed over the upper substrate and configured to transmit the incident light to the pixel region, an insulation layer disposed between the upper substrate and the lower substrate, a light reception alignment mark disposed in the first peripheral region and configured to assist positioning of the light reception elements, and an alignment pattern disposed between the first peripheral region and the second peripheral region and in the insulation layer. The alignment pattern is configured to absorb light used to measure the light reception alignment mark.

Abstract: An image sensing device is disclosed. The image sensing device includes a substrate, an array of unit pixels and a grid structure formed over the substrate and between adjacent unit pixels to prevent crosstalk between contiguous unit pixels. The grid structure includes a pixel grid region in which first light shielding patterns extending in a first direction and second light shielding patterns extending in a second direction perpendicular to the first direction are arranged to cross each other, and an open grid region coupled to the pixel grid region and including first light shielding patterns extending in the first direction and second light shielding patterns extending in the second direction, the first light shielding patterns and the second light shielding patterns arranged not to cross each other. The first light shielding patterns and the second light shielding patterns include an air layer and a capping layer disposed over the air layer.

Abstract: An image sensor may include: photoelectric conversion elements formed in a substrate, and isolation regions disposed between the photoelectric conversion elements; an anti-reflective layer formed over the substrate; grid patterns formed over the anti-reflective layer; color filters between the grid patterns; and microlenses formed over the color filters. Each of the grid patterns may include an upper grid portion and a lower grid portion, and the bottom of the lower grid portion is embedded in the anti-reflective layer.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a transfer-receiving substrate having a high region and a low region that are different in top-surface height from each other, a transfer-receiving pattern layer formed over the high region and the low region of the transfer-receiving substrate, in a manner that a top surface of the transfer-receiving pattern layer in the high region is planarized and a top surface of the transfer-receiving pattern layer in the low region is provided with a concave-convex pattern, and a planarization layer formed to gapfill the concave-convex pattern in a manner that a top surface of the planarization layer in the high region and a top surface of the planarization layer in the low region are planarized at a substantially same level.

Abstract: An image sensing device for minimizing light reflected from a light shielding layer is disclosed. The image sensing device includes a semiconductor layer formed to include an active pixel region and an optical black pixel region, a light shielding layer located at the optical black pixel region formed over the semiconductor layer, a first color filter layer located at the active pixel region formed over the semiconductor layer, and a second color filter layer located over the light shielding layer. Each of the first and second color filter layers includes at least one first color filter, at least one second color filter, and at least one third color filter. In the first color filter layer, the first color filter, the second color filter, and the third color filter are arranged in the same layer.

Abstract: An image sensing device capable of minimizing reflection of light incident upon a metal layer is disclosed. The image sensing device includes a semiconductor substrate in which at least one groove is formed, a reflection prevention layer formed over the semiconductor substrate in a manner that the at least one groove is buried by the reflection prevention layer, and a metal layer formed over the reflection prevention layer, and provided with at least one through-hole corresponding to the at least one groove.

Abstract: An image sensing device for minimizing light reflected from a light shielding layer is disclosed. The image sensing device includes a semiconductor layer formed to include an active pixel region and an optical black pixel region, a light shielding layer located at the optical black pixel region formed over the semiconductor layer, a first color filter layer located at the active pixel region formed over the semiconductor layer, and a second color filter layer located over the light shielding layer. Each of the first and second color filter layers includes at least one first color filter, at least one second color filter, and at least one third color filter. In the first color filter layer, the first color filter, the second color filter, and the third color filter are arranged in the same layer.

Abstract: An image sensor may include: photoelectric conversion elements formed in a substrate, and isolation regions disposed between the photoelectric conversion elements; an anti-reflective layer formed over the substrate; grid patterns formed over the anti-reflective layer; color filters between the grid patterns; and microlenses formed over the color filters. Each of the grid patterns may include an upper grid portion and a lower grid portion, and the bottom of the lower grid portion is embedded in the anti-reflective layer.

Abstract: A semiconductor device including a first stacked structure including first conductive layers and first insulating layers stacked alternately with each other, first semiconductor patterns arranged in a first direction, wherein each of the first semiconductor patterns passes through the first stacked structure in a stacking direction, a second stacked structure including second conductive layers and second insulating layers stacked alternately with each other, second semiconductor patterns arranged in the first direction and adjacent to the first semiconductor patterns in a second direction crossing the first direction, wherein each of the second semiconductor patterns passes through the second stacked structure in the stacking direction, a third stacked structure including air gaps and third insulating layers stacked alternately with each other and located between the first and second structures, and at least one blocking pattern passing through the third stacked structure in the stacking direction and contact

Abstract: A method of forming patterns is provided. The method includes forming a resist layer on a substrate, forming a lattice-shaped extrusion barrier region in the resist layer to define pattern transfer regions corresponding to a plurality of separate windows, and positioning a template on the resist layer so that a patterned surface of the template faces the resist layer. The patterned surface provides a plurality of transfer patterns. The template is pressed to perform an imprint step for embedding the transfer patterns of the template into the pattern transfer regions of the resist layer.

Abstract: A method for forming patterns is provided. The method includes forming a resist layer on a substrate, imprinting a convex pattern and a concave pattern on the resist layer using a template, forming a silicon diffusion layer containing silicon containing diffusion species in an upper portion of the convex pattern, and selectively removing a recessed portion of the resist layer under the concave pattern using the silicon diffusion layer as an etch mask.

Abstract: A method for forming patterns is provided. The method includes forming a resist layer on a substrate, imprinting a convex pattern and a concave pattern on the resist layer using a template, forming a silicon diffusion layer containing silicon containing diffusion species in an upper portion of the convex pattern, and selectively removing a recessed portion of the resist layer under the concave pattern using the silicon diffusion layer as an etch mask.

Abstract: A method of forming patterns is provided. The method includes forming a resist layer on a substrate, imprinting transfer patterns of a template on the resist layer, performing an alignment operation to correct a position of the substrate or the template, increasing a viscosity of the resist layer while the alignment operation is performed, and curing the resist layer after the alignment operation terminates.

Abstract: A method of forming patterns is provided. The method includes forming a resist layer on a substrate, forming a lattice-shaped extrusion barrier region in the resist layer to define pattern transfer regions corresponding to a plurality of separate windows, and positioning a template on the resist layer so that a patterned surface of the template faces the resist layer. The patterned surface provides a plurality of transfer patterns. The template is pressed to perform an imprint step for embedding the transfer patterns of the template into the pattern transfer regions of the resist layer.

Abstract: A semiconductor device including a first stacked structure including first conductive layers and first insulating layers stacked alternately with each other, first semiconductor patterns arranged in a first direction, wherein each of the first semiconductor patterns passes through the first stacked structure in a stacking direction, a second stacked structure including second conductive layers and second insulating layers stacked alternately with each other, second semiconductor patterns arranged in the first direction and adjacent to the first semiconductor patterns in a second direction crossing the first direction, wherein each of the second semiconductor patterns passes through the second stacked structure in the stacking direction, a third stacked structure including air gaps and third insulating layers stacked alternately with each other and located between the first and second structures, and at least one blocking pattern passing through the third stacked structure in the stacking direction and contact

Abstract: A semiconductor device includes a stacked structure including conductive layers and insulating layers stacked alternately with each other, first semiconductor patterns passing through the stacked structure and arranged in a first direction, second semiconductor patterns passing through the stacked structure and arranged in the first direction, wherein the second semiconductor patterns are adjacent to the first semiconductor patterns in a second direction crossing the first direction, air gaps located between the first semiconductor patterns and the second semiconductor patterns and extending in the first direction, and at least one blocking pattern passing through the stacked structure and filling portions of the air gaps.

Abstract: An alignment key of a semiconductor device includes: a material layer formed at a scribe region of a semiconductor substrate, a first dummy hole and a second dummy hole passing through the material layers, a first channel insulation layer formed inside the first dummy hole, a second channel insulation layer formed inside the second dummy hole, a first capping layer formed on a side wall of an upper portion of the first dummy hole and an upper portion of the first channel insulation layer, and a second capping layer formed on a side wall of an upper portion of the second dummy hole and an upper portion of the channel insulation layer, having a height of a lower surface portion greater than that of a lower surface portion of the first capping layer.

Abstract: A method of manufacturing a semiconductor device includes forming stepped stack structures each including conductive patterns stacked in a shape of steps while exposing respective ends thereof and surrounding channel layers, the stepped stack structures being separated from one another by slits, forming first and second contact plugs connected to the ends of the conductive patterns to extend along an extending direction of the channel layers, and simultaneously forming, using a spacer patterning technology (SPT), bit lines connected to one or more of the channel layers and extending along a first direction, first connecting lines extending along a second direction intersecting the first direction, and contact pads extending from the first connecting lines to be connected to the first contact plugs.

Abstract: A method of manufacturing a semiconductor device includes forming stepped stack structures each including conductive patterns stacked in a shape of steps while exposing respective ends thereof and surrounding channel layers, the stepped stack structures being separated from one another by slits, forming first and second contact plugs connected to the ends of the conductive patterns to extend along an extending direction of the channel layers, and simultaneously forming, using a spacer patterning technology (SPT), bit lines connected to one or more of the channel layers and extending along a first direction, first connecting lines extending along a second direction intersecting the first direction, and contact pads extending from the first connecting lines to be connected to the first contact plugs.