Patents by Inventor Xaver Schloegel
Xaver Schloegel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230230903Abstract: A semiconductor chip is provided. The semiconductor chip may include a front side including a control chip contact and a first controlled chip contact, a back side including a second controlled chip contact, a backside metallization formed over the back side in contact with the second controlled chip contact, and a stop region extending at least partially along an outer edge of the back side between a contact portion of the backside metallization and the outer edge of the back side. The contact portion is configured to be attached to an electrically conductive structure by a die attach material, a surface of the stop region is recessed with respect to a surface of the contact portion, and/or the surface of the stop region has a lower wettability with respect to the die attach material than the contact portion.Type: ApplicationFiled: December 21, 2022Publication date: July 20, 2023Applicant: Infineon Technologies AGInventors: Hooi Boon TEOH, Hao ZHUANG, Oliver BLANK, Paul Armand CALO, Markus DINKEL, Josef Höglauer, Daniel Hölzl, Wee Aun JASON LIM, Gerhard Thomas Nöbauer, Ralf OTREMBA, Martin Pölzl, Ying Pok SAM, Xaver Schlögel, Chee Voon TAN
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Patent number: 11676881Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a chip carrier, a semiconductor chip attached to the chip carrier, an encapsulation body encapsulating the semiconductor chip, and a mounting hole configured to receive a screw for screw mounting a heatsink onto a first side of the semiconductor package. A second side of the semiconductor package opposite the first side is configured to be surface mounted to an application board.Type: GrantFiled: July 15, 2020Date of Patent: June 13, 2023Assignee: Infineon Technologies AGInventors: Ralf Otremba, Teck Sim Lee, Klaus Schiess, Xaver Schloegel, Lee Shuang Wang, Mohd Hasrul Zulkifli
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Publication number: 20230127874Abstract: A power semiconductor system includes: a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board; and an inductor module attached to the power stage module and having an inductor electrically connected to an output node of the power stage module. The inductor includes windings patterned into a second printed circuit board of the inductor module.Type: ApplicationFiled: December 22, 2022Publication date: April 27, 2023Inventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
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Patent number: 11539291Abstract: A method of manufacturing a power semiconductor system includes providing a power module having one or more power transistor dies and attaching an inductor module to the power module such that the inductor module is electrically connected to a node of the power module. The inductor module includes a substrate with a magnetic material and windings at one or more sides of the substrate. Further methods of manufacturing power semiconductor systems and methods of manufacturing inductor modules are also described.Type: GrantFiled: October 20, 2020Date of Patent: December 27, 2022Assignee: Infineon Technologies Austria AGInventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
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Publication number: 20210036610Abstract: A method of manufacturing a power semiconductor system includes providing a power module having one or more power transistor dies and attaching an inductor module to the power module such that the inductor module is electrically connected to a node of the power module. The inductor module includes a substrate with a magnetic material and windings at one or more sides of the substrate. Further methods of manufacturing power semiconductor systems and methods of manufacturing inductor modules are also described.Type: ApplicationFiled: October 20, 2020Publication date: February 4, 2021Inventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
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Patent number: 10903133Abstract: A package encloses a power semiconductor die and has a package body with a top side, footprint side and sidewalls. The die has first and second load terminals and blocks a blocking voltage between the load terminals. The package further includes: a lead frame structure for electrically and mechanically coupling the package to a support, the lead frame structure including an outside terminal extending out of the package footprint side and/or out of one of the package sidewalls and electrically connected with the first load terminal; and a top layer arranged at the package top side and electrically connected with the second load terminal. A heat spreader is mounted onto the top layer with a bottom surface facing the top layer. The area of the top surface of the heat spreader is greater than the area of the bottom surface.Type: GrantFiled: January 8, 2020Date of Patent: January 26, 2021Assignee: Infineon Technologies Austria AGInventors: Ralf Otremba, Markus Dinkel, Ulrich Froehler, Josef Hoeglauer, Uwe Kirchner, Guenther Lohmann, Klaus Schiess, Xaver Schloegel
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Publication number: 20210020539Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a chip carrier, a semiconductor chip attached to the chip carrier, an encapsulation body encapsulating the semiconductor chip, and a mounting hole configured to receive a screw for screw mounting a heatsink onto a first side of the semiconductor package. A second side of the semiconductor package opposite the first side is configured to be surface mounted to an application board.Type: ApplicationFiled: July 15, 2020Publication date: January 21, 2021Applicant: Infineon Technologies AGInventors: Ralf Otremba, Teck Sim Lee, Klaus Schiess, Xaver Schloegel, Lee Shuang Wang, Mohd Hasrul Zulkifli
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Patent number: 10886186Abstract: A semiconductor package system comprises a semiconductor package and a cap. The semiconductor package comprises a die pad, a chip mounted or arranged to a first main face of the die pad and an encapsulation body encapsulating the chip and the die pad. The cap covers at least partly an exposed second main face of the die pad. The cap comprises a cap body of an electrically insulating and thermally conductive material and a fastening system fastening the cap to the semiconductor package. The fastening system extends from the cap body towards the encapsulation body or along a side surface of the semiconductor package.Type: GrantFiled: March 27, 2019Date of Patent: January 5, 2021Assignee: Infineon Technologies AGInventors: Thorsten Scharf, Ralf Otremba, Thomas Bemmerl, Irmgard Escher-Poeppel, Martin Gruber, Michael Juerss, Thorsten Meyer, Xaver Schloegel
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Patent number: 10833583Abstract: A method of manufacturing a power semiconductor system includes providing a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board and attaching an inductor module to the power stage module such that the inductor module is electrically connected to an output node of the power stage module. The inductor module includes a ferrite sheet embedded in a second printed circuit board and windings patterned into the second printed circuit board. Further methods of manufacturing power semiconductor systems and methods of manufacturing inductor modules are also described.Type: GrantFiled: March 6, 2020Date of Patent: November 10, 2020Assignee: Infineon Technologies Austria AGInventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
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Publication number: 20200212798Abstract: A method of manufacturing a power semiconductor system includes providing a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board and attaching an inductor module to the power stage module such that the inductor module is electrically connected to an output node of the power stage module. The inductor module includes a ferrite sheet embedded in a second printed circuit board and windings patterned into the second printed circuit board. Further methods of manufacturing power semiconductor systems and methods of manufacturing inductor modules are also described.Type: ApplicationFiled: March 6, 2020Publication date: July 2, 2020Inventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
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Patent number: 10700037Abstract: In some examples, a device includes a semiconductor element, a layer element, and a single connector element electrically connecting the semiconductor element and the layer element. In some examples, the single connector element includes two or more discrete connector elements, and each discrete connector element of the two or more discrete connector elements electrically connects the semiconductor element and the layer element. In some examples, the single connector element also includes conductive material attached to the two or more discrete connector elements.Type: GrantFiled: November 13, 2017Date of Patent: June 30, 2020Assignee: Infineon Technologies AGInventors: Eung San Cho, Thorsten Meyer, Xaver Schloegel, Thomas Behrens, Josef Hoeglauer
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Patent number: 10699987Abstract: A package encloses a power semiconductor die that has a first load terminal at a die frontside facing a footprint side of the package and a second load terminal arranged at a die backside facing a top side of the package. The package also includes a lead frame configured to electrically and mechanically couple the package to a support. The lead frame has a planar first outside terminal electrically connected with the first load terminal and a planar second outside terminal electrically connected with the second load terminal. The planar first outside terminal is configured to interface with the support by means of a first contact area. The planar second outside terminal is configured to interface with the support by means of a second contact area. The second contact area has a size in a range between 80% and 120% of a size of the first contact area.Type: GrantFiled: April 16, 2018Date of Patent: June 30, 2020Assignee: tInfineon Technologies Austria AGInventors: Ralf Otremba, Chooi Mei Chong, Markus Dinkel, Josef Hoeglauer, Klaus Schiess, Xaver Schloegel
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Patent number: 10699978Abstract: A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals for blocking a blocking voltage. A lead frame structure electrically and mechanically couples the package to a support and includes an outside terminal extending out of the package footprint side and/or the sidewalls, and is electrically connected with the first load terminal. A top layer arranged at the package top side is electrically connected with the second load terminal. A creepage length between the electrical potential of the outside terminal and the electrical potential of the top layer is defined by a package body surface contour. The surface contour is formed at least by the package top side and package sidewall. At least one structural feature also forms the surface contour is configured to increase the creepage length.Type: GrantFiled: September 7, 2018Date of Patent: June 30, 2020Assignee: Infineon Technologies Austria AGInventors: Ralf Otremba, Amirul Afiq Hud, Teck Sim Lee, Xaver Schloegel, Bernd Schmoelzer
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Publication number: 20200144150Abstract: A package encloses a power semiconductor die and has a package body with a top side, footprint side and sidewalls. The die has first and second load terminals and blocks a blocking voltage between the load terminals. The package further includes: a lead frame structure for electrically and mechanically coupling the package to a support, the lead frame structure including an outside terminal extending out of the package footprint side and/or out of one of the package sidewalls and electrically connected with the first load terminal; and a top layer arranged at the package top side and electrically connected with the second load terminal. A heat spreader is mounted onto the top layer with a bottom surface facing the top layer. The area of the top surface of the heat spreader is greater than the area of the bottom surface.Type: ApplicationFiled: January 8, 2020Publication date: May 7, 2020Inventors: Ralf Otremba, Markus Dinkel, Ulrich Froehler, Josef Hoeglauer, Uwe Kirchner, Guenther Lohmann, Klaus Schiess, Xaver Schloegel
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Patent number: 10601314Abstract: A power semiconductor system includes a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board, and an inductor module attached to the power stage module and having an inductor electrically connected to an output node of the power stage module. The inductor is formed from a ferrite sheet embedded in a second printed circuit board and windings patterned into the second printed circuit board. Corresponding methods of manufacturing the power semiconductor system and the inductor module are also disclosed.Type: GrantFiled: September 8, 2017Date of Patent: March 24, 2020Assignee: Infineon Technologies Austria AGInventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
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Publication number: 20200083207Abstract: A method of manufacturing a semiconductor device includes mounting a first semiconductor power chip on a first carrier, mounting a second semiconductor power chip on a second carrier, bonding a contact clip to the first semiconductor power chip and to the second semiconductor power chip, and mounting a third semiconductor chip over the contact clip.Type: ApplicationFiled: November 14, 2019Publication date: March 12, 2020Inventors: Ralf Otremba, Josef Hoeglauer, Xaver Schloegel, Chooi Mei Chong
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Patent number: 10566260Abstract: A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals and blocks a blocking voltage between the load terminals. The package further includes: a lead frame structure for electrically and mechanically coupling the package to a support, the lead frame structure including an outside terminal extending out of the package footprint side and/or out of one of the package sidewalls and electrically connected with the first load terminal; a top layer arranged at the package top side and electrically connected with the second load terminal; and a heat spreader arranged external of the package body and in electrical contact with the top layer. A top surface of the heat spreader has an area greater than the area of the bottom surface.Type: GrantFiled: September 7, 2018Date of Patent: February 18, 2020Assignee: Infineon Technologies Austria AGInventors: Ralf Otremba, Markus Dinkel, Ulrich Froehler, Josef Hoeglauer, Uwe Kirchner, Guenther Lohmann, Klaus Schiess, Xaver Schloegel
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Publication number: 20190304858Abstract: A semiconductor package system comprises a semiconductor package and a cap. The semiconductor package comprises a die pad, a chip mounted or arranged to a first main face of the die pad and an encapsulation body encapsulating the chip and the die pad. The cap covers at least partly an exposed second main face of the die pad. The cap comprises a cap body of an electrically insulating and thermally conductive material and a fastening system fastening the cap to the semiconductor package. The fastening system extends from the cap body towards the encapsulation body or along a side surface of the semiconductor package.Type: ApplicationFiled: March 27, 2019Publication date: October 3, 2019Applicant: Infineon Technologies AGInventors: Thorsten Scharf, Ralf Otremba, Thomas Bemmerl, Irmgard Escher-Poeppel, Martin Gruber, Michael Juerss, Thorsten Meyer, Xaver Schloegel
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Publication number: 20190148332Abstract: In some examples, a device includes a semiconductor element, a layer element, and a single connector element electrically connecting the semiconductor element and the layer element. In some examples, the single connector element includes two or more discrete connector elements, and each discrete connector element of the two or more discrete connector elements electrically connects the semiconductor element and the layer element. In some examples, the single connector element also includes conductive material attached to the two or more discrete connector elements.Type: ApplicationFiled: November 13, 2017Publication date: May 16, 2019Applicant: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Thorsten Meyer, Xaver Schloegel, Thomas Behrens, Josef Hoeglauer
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Publication number: 20190080973Abstract: A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals for blocking a blocking voltage. A lead frame structure electrically and mechanically couples the package to a support and includes an outside terminal extending out of the package footprint side and/or the sidewalls, and is electrically connected with the first load terminal. A top layer arranged at the package top side is electrically connected with the second load terminal. A creepage length between the electrical potential of the outside terminal and the electrical potential of the top layer is defined by a package body surface contour. The surface contour is formed at least by the package top side and package sidewall. At least one structural feature also forms the surface contour is configured to increase the creepage length.Type: ApplicationFiled: September 7, 2018Publication date: March 14, 2019Inventors: Ralf Otremba, Amirul Afiq Hud, Teck Sim Lee, Xaver Schloegel, Bernd Schmoelzer