Patents by Inventor Xavier GARROS

Xavier GARROS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9689913
    Abstract: A method for measuring the changes of the electrical performance of an FDSOI transistor between a first and a second state of the transistor after an operating period t1, including the following steps: measurement of the transistor's capacities C1 and C2 respectively in the first and second states, according to a voltage VFG applied between the gate and the source and drain areas, determination, in relation to characteristic C1(VFG) varying between a maximum value Cmax and a minimum value Cmin, with three inflection points, of an ordinate value Cplat of C1(VFG) at the second inflection point of C1(VFG), and of two abscissa values VUpper(0) and VLower(0) of C1(VFG) according to equations VUpper(0)=C1?1((Cmax+Cplat)/2) and VLower(0)=C1?1((Cmin+Cplat)/2), determination, from characteristic C2(VFG), of two abscissa values VUpper(t1) and VLower(t1) of C2(VFG) according to equations VUpper(t1)=C2?1((Cmax+Cplat)/2) and VLower(t1)=C2?1((Cmin+Cplat)/2), determination of variations of defect densities ?Dit1, ?Dit2 b
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: June 27, 2017
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Xavier Garros, Laurent Brunet
  • Patent number: 8525528
    Abstract: A method for evaluating the electric performances of an FDSOI transistor, including the steps of: measuring capacitance and/or conductance of the FDSOI transistor, by applying a voltage VBG>0 on a substrate composed of semiconductor of the FDSOI transistor when the FDSOI transistor is NMOS or a voltage VBG<0 on the substrate composed of semiconductor of the FDSOI transistor when the FDSOI transistor is PMOS, depending on a voltage VFG applied between a gate and source and drain regions of the FDSOI transistor.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: September 3, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Xavier Garros, Laurent Brunet
  • Publication number: 20110050253
    Abstract: A method for evaluating the electric performances of an FDSOI transistor, including the steps of: measuring the capacitance and/or the conductance of the FDSOI transistor, by applying a rear voltage VBG>0 or VBG<0 on the substrate of the transistor, depending on a front voltage VFG applied on the gate of the transistor, calculating the theoretical values of the capacitance and/or the conductance of a transistor modeled by an electric circuit equivalent to the FDSOI transistor, for different selected theoretical values of defect densities Dit1, Dit2 at the dielectric-semiconductor interfaces of the modeled transistor, determining the real values of Dit1, Dit2 at the corresponding interfaces of the FDSOI transistor by a comparison between the measured values of the capacitance and/or the conductance of the FDSOI transistor and the calculated theoretical values of the capacitance and/or the conductance of the modeled transistor.
    Type: Application
    Filed: August 20, 2010
    Publication date: March 3, 2011
    Applicant: Comm. a l' ener. atom. et aux energies alter.
    Inventors: Xavier GARROS, Laurent BRUNET