Abstract: The present disclosure provides a display panel and an array substrate. The array substrate includes a plurality of pixels forming a plurality of pixel columns, and one pixel includes a plurality of sub-pixels. The array substrate includes: a substrate; a pixel electrode layer, including a plurality of pixel electrodes in one-to-one correspondence with the plurality of sub-pixels; a touch electrode layer, disposed at a side of the pixel electrode layer, where the touch electrode layer includes a plurality of touch electrode cells spaced apart and mutually insulated; where there is a first gap between two t touch electrode cells that are adjacent in a direction of the pixel columns, and the first gap is located between both ends of a pixel electrode along the direction of the pixel columns.

Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate and a plurality of shift register units; each of the plurality of shift register units includes an input circuit, an output circuit, a first reset circuit and a frame reset signal connection wire; the frame reset signal connection wire and is configured to provide a frame reset signal to the first reset circuit; the first reset circuit is configured to respond to the frame reset signal, so as to reset a first node and an output end within a time period between two display frames of the display substrate; the first reset circuit includes a first transistor and a second transistor, and the frame reset signal connection wire, a gate of the first transistor and a gate of the second transistor are provided on a first conductive layer.

Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate and a plurality of shift register units; each of the plurality of shift register units includes an input circuit, an output circuit, a first reset circuit and a frame reset signal connection wire; the frame reset signal connection wire and is configured to provide a frame reset signal to the first reset circuit; the first reset circuit is configured to respond to the frame reset signal, so as to reset a first node and an output end within a time period between two display frames of the display substrate; the first reset circuit includes a first transistor and a second transistor, and the frame reset signal connection wire, a gate of the first transistor and a gate of the second transistor are provided on a first conductive layer.

Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate and a plurality of shift register units; each of the plurality of shift register units includes an input circuit, an output circuit, a first reset circuit and a frame reset signal connection wire; the frame reset signal connection wire and is configured to provide a frame reset signal to the first reset circuit; the first reset circuit is configured to respond to the frame reset signal, so as to reset a first node and an output end within a time period between two display frames of the display substrate; the first reset circuit includes a first transistor and a second transistor, and the frame reset signal connection wire, a gate of the first transistor and a gate of the second transistor are provided on a first conductive layer.

Abstract: Disclosed is a display panel including: first spacer on the array substrate, an orthographic projection of the first spacer on the array substrate being a first pattern extending along a first direction; a second spacer on the counter substrate, an orthographic projection of the second spacer on the array substrate being a second pattern extending along a second direction; at least two third spacers, orthographic projections of which on the array substrate being respectively on two sides of the first pattern along the first direction; at least two fourth spacers, orthographic projections of which on the array substrate being respectively on two sides of the second pattern along the second direction; one of the third spacer and the fourth spacer is on the array substrate, and the other is on the counter substrate.

Abstract: Disclosed are a gate driving circuit and a display device. According to the gate driving circuit, in every five adjacent shift registers, the output control end of the first shift register is electrically connected to the input signal end of the fifth shift register; in every six adjacent shift registers, the output control end of the sixth shift register is electrically connected to the reset signal end of the first shift register.

Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate and a plurality of shift register units; each of the plurality of shift register units includes an input circuit, an output circuit, a first reset circuit and a frame reset signal connection wire; the frame reset signal connection wire and is configured to provide a frame reset signal to the first reset circuit; the first reset circuit is configured to respond to the frame reset signal, so as to reset a first node and an output end within a time period between two display frames of the display substrate; the first reset circuit includes a first transistor and a second transistor, and the frame reset signal connection wire, a gate of the first transistor and a gate of the second transistor are provided on a first conductive layer.

Abstract: Provided is a display panel. The display panel comprises an array substrate and a color filter substrate, wherein the color filter substrate comprises a second substrate and a black matrix pattern, wherein the black matrix pattern comprises a body, via hole shielding parts, and compensation shielding parts, the via hole shielding parts being disposed within first domains of part of plurality of sub-pixel regions, the compensation shielding parts being disposed within second domains that are adjacent in first direction to the first domains where the via hole shielding parts are disposed, and at most one of the via hole shielding part and the compensation shielding part being disposed in one sub-pixel region.

Abstract: Embodiments of the present disclosure provide a display panel, a preparing method, and a display device. The display panel includes: a color film substrate and an array substrate opposite to the color film substrate. The color film substrate includes: an opposite substrate, a color resistance layer on the opposite substrate and a plurality of support structures on a side, away from the opposite substrate, of the color resistance layer at intervals. The array substrate includes: a base substrate and a plurality of auxiliary structures on a side, facing the opposite substrate, of the base substrate at intervals. At least one auxiliary structure of the plurality of auxiliary structures correspondingly contacts with at least one support structure of the plurality of support structures.

Abstract: A selection circuit, a method for controlling the selection circuit, and a multiplexing circuit are provided. The selection circuit includes N control circuits and M booster circuits. Control terminals of M control circuits among the N control circuits are coupled to output terminals of the M booster circuits, respectively, and first input terminals of the M booster circuits are coupled to receive M control signals among N control signals, respectively. Second input terminals of the M booster circuits are coupled to receive M boost signals respectively, and each booster circuit is configured to provide the received control signal to an output terminal of the booster circuit and increase a potential at the output terminal of the booster circuit by using the received boost signal.

Abstract: Provided are a shift register, a driving method thereof, and a gate driving circuit. The shift register includes an input sub-circuit, a first reset sub-circuit, an output sub-circuit, a pull-down sub-circuit, a pull-down control sub-circuit, and a second reset sub-circuit. The input sub-circuit provides a signal of the first voltage source to the pull-up node and the first node under the control of the signal input terminal; the first reset sub-circuit provides a signal of the second voltage source to the pull-up node and the first node under the control of the reset terminal; the output sub-circuit outputs the signal of the clock signal terminal to the signal output terminal according to the level of the pull-up node.

Abstract: The present disclosure provides a shift register, a gate driving circuit and a display panel, and belongs to the field of display technology. The shift register of the present disclosure includes: an input circuit configured to precharge and reset a pull-up node; one pull-down control circuit being electrically connected to one pull-down circuit through a pull-down node; the pull-down control circuit being configured to control a potential at the pull-down node under a first power voltage; each pull-down circuit being configured to pull down the potential at the pull-down node in response to a potential at the pull-up node; an output circuit configured to output a clock signal through a signal output terminal in response to the potential at the pull-up node; one first noise reduction circuit connected to one pull-down node.

Abstract: The present disclosure provides a shift register, a gate driving circuit and a display panel, and belongs to the field of display technology. The shift register of the present disclosure includes: an input circuit configured to precharge and reset a pull-up node; one pull-down control circuit being electrically connected to one pull-down circuit through a pull-down node; the pull-down control circuit being configured to control a potential at the pull-down node under a first power voltage; each pull-down circuit being configured to pull down the potential at the pull-down node in response to a potential at the pull-up node; an output circuit configured to output a clock signal through a signal output terminal in response to the potential at the pull-up node; one first noise reduction circuit connected to one pull-down node.

Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate and a plurality of shift register units; each of the plurality of shift register units includes an input circuit, an output circuit, a first reset circuit and a frame reset signal connection wire; the frame reset signal connection wire and is configured to provide a frame reset signal to the first reset circuit; the first reset circuit is configured to respond to the frame reset signal, so as to reset a first node and an output end within a time period between two display frames of the display substrate; the first reset circuit includes a first transistor and a second transistor, and the frame reset signal connection wire, a gate of the first transistor and a gate of the second transistor are provided on a first conductive layer.

Abstract: Disclosed are a gate driving circuit and a display device. According to the gate driving circuit, in every five adjacent shift registers, the output control end of the first shift register is electrically connected to the input signal end of the fifth shift register; in every six adjacent shift registers, the output control end of the sixth shift register is electrically connected to the reset signal end of the first shift register.

Abstract: Provided is a display panel. The display panel comprises an array substrate and a color filter substrate, wherein the color filter substrate comprises a second substrate and a black matrix pattern, wherein the black matrix pattern comprises a body, via hole shielding parts, and compensation shielding parts, the via hole shielding parts being disposed within first domains of part of plurality of sub-pixel regions, the compensation shielding parts being disposed within second domains that are adjacent in first direction to the first domains where the via hole shielding parts are disposed, and at most one of the via hole shielding part and the compensation shielding part being disposed in one sub-pixel region.

Abstract: A display substrate has a display area and an encapsulation area around the display area. The display substrate includes a substrate and a spacer layer. The spacer layer is located on a side of the substrate, and includes a plurality of first columnar spacers located in the encapsulation area and distributed at intervals around the display area, and bottom ends of the plurality of first columnar spacers are fixedly disposed on the substrate. Ends of the plurality of first columnar spacers proximate to the substrate are the bottom ends thereof, and ends of the plurality of first columnar spacers away from the substrate are top ends thereof.

Abstract: Embodiments of the present disclosure provide a display panel, a preparing method, and a display device. The display panel includes: a color film substrate and an array substrate opposite to the color film substrate. The color film substrate includes: an opposite substrate, a color resistance layer on the opposite substrate and a plurality of support structures on a side, away from the opposite substrate, of the color resistance layer at intervals. The array substrate includes: a base substrate and a plurality of auxiliary structures on a side, facing the opposite substrate, of the base substrate at intervals. At least one auxiliary structure of the plurality of auxiliary structures correspondingly contacts with at least one support structure of the plurality of support structures.

Abstract: An array substrate has a plurality of sub-pixel regions, and each sub-pixel region includes an opening region and a pixel defining region surrounding the opening region. The array substrate includes a base and a plurality of touch signal lines disposed on the base. An orthographic projection of at least one touch signal line on the base passes through, along an extending direction thereof, at least one opening region.

Abstract: Provided are a shift register, a driving method thereof, and a gate driving circuit. The shift register includes an input sub-circuit, a first reset sub-circuit, an output sub-circuit, a pull-down sub-circuit, a pull-down control sub-circuit, and a second reset sub-circuit. The input sub-circuit provides a signal of the first voltage source to the pull-up node and the first node under the control of the signal input terminal; the first reset sub-circuit provides a signal of the second voltage source to the pull-up node and the first node under the control of the reset terminal; the output sub-circuit outputs the signal of the clock signal terminal to the signal output terminal according to the level of the pull-up node.