Patents by Inventor Xiaodong Jin

Xiaodong Jin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10991065
    Abstract: Method, system, and computer readable medium for processing graphics using an OpenGL Embedded Systems Application Programming Interface (Open GLES API) include: decoding a source graphic to generate a graphic object, where the graphic object includes a set of index values and a color palette; providing the graphic object to a Graphical Processing Unit (GPU) through the Open GLES API, including providing the set of index values in a first acceptable graphic format of the Open GLES API to the GPU, and providing the color palette in a second acceptable graphic format of the Open GLES API to the GPU; and triggering the GPU to render the source graphic according to the set of index values received in the first acceptable graphic format of Open GLES API and the palette received in the second acceptable graphic format of Open GLES API.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: April 27, 2021
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventor: Xiaodong Jin
  • Patent number: 10851432
    Abstract: The present invention discloses an ultra-high strength and ultra-high toughness casing steel, having a microstructure of tempered sorbite, and the content of chemical elements by mass percent thereof being as follows: C: 0.1-0.22%, Si: 0.1-0.4%, Mn: 0.5-1.5%, Cr: 1-1.5%, Mo: 1-1.5%, Nb: 0.01-0.04%, V: 0.2-0.3%, Al: 0.01-0.05%, Ca: 0.0005-0.005%, the balance being Fe and unavoidable impurities. Correspondingly, the invention also discloses a casing obtained by processing the ultra-high strength and ultra-high toughness casing steel and a manufacturing method thereof. The ultra-high strength and ultra-toughness casing steel and the casing of the present invention have a strength of 155 ksi or more and an impact toughness greater than 10% of its yield strength value, thereby realizing a combination of ultra-high strength and ultra-high toughness.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: December 1, 2020
    Assignee: BAOSHAN IRON & STEEL CO., LTD.
    Inventors: Xiaoming Dong, Zhonghua Zhang, Xiaodong Jin
  • Publication number: 20200043126
    Abstract: Method, system, and computer readable medium for processing graphics using an OpenGL Embedded Systems Application Programming Interface (Open GLES API) include: decoding a source graphic to generate a graphic object, where the graphic object includes a set of index values and a color palette; providing the graphic object to a Graphical Processing Unit (GPU) through the Open GLES API, including providing the set of index values in a first acceptable graphic format of the Open GLES API to the GPU, and providing the color palette in a second acceptable graphic format of the Open GLES API to the GPU; and triggering the GPU to render the source graphic according to the set of index values received in the first acceptable graphic format of Open GLES API and the palette received in the second acceptable graphic format of Open GLES API.
    Type: Application
    Filed: October 10, 2019
    Publication date: February 6, 2020
    Inventor: Xiaodong JIN
  • Publication number: 20180291475
    Abstract: The present invention discloses an ultra-high strength and ultra-high toughness casing steel, having a microstructure of tempered sorbite, and the content of chemical elements by mass percent thereof being as follows: C: 0.1-0.22%, Si: 0.1-0.4%, Mn: 0.5-1.5%, Cr: 1-1.5%, Mo: 1-1.5%, Nb: 0.01-0.04%, V: 0.2-0.3%, Al: 0.01-0.05%, Ca: 0.0005-0.005%, the balance being Fe and unavoidable impurities. Correspondingly, the invention also discloses a casing obtained by processing the ultra-high strength and ultra-high toughness casing steel and a manufacturing method thereof. The ultra-high strength and ultra-toughness casing steel and the casing of the present invention have a strength of 155 ksi or more and an impact toughness greater than 10% of its yield strength value, thereby realizing a combination of ultra-high strength and ultra-high toughness.
    Type: Application
    Filed: June 17, 2016
    Publication date: October 11, 2018
    Inventors: Xiaoming DONG, Zhonghua ZHANG, Xiaodong JIN
  • Patent number: 8781539
    Abstract: A method includes, in at least one aspect, connecting an input of a bias circuit and an output of the bias circuit to another circuit while the other circuit is in a first power mode, such that the bias circuit has an operating state corresponding to the first power mode; switching the input of the bias circuit and the output of the bias circuit from the other circuit to a dummy circuit when a power mode of the other circuit is changed from the first power mode to a second power mode; and maintaining the bias circuit at the operating state corresponding to the first power mode using the dummy circuit while the other circuit is in the second power mode.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: July 15, 2014
    Assignee: Marvell International Ltd.
    Inventors: Xiaodong Jin, King Chun Tsai, Yonghua Song
  • Patent number: 8595538
    Abstract: In an embodiment of the present invention, a clock generator circuit is disclosed to include a phase locked loop (PLL) that is responsive to a reference frequency and operative to generate a single clock frequency and a clock signal quadrature output frequency and a clock signal in-phase output with the frequency of the clock signal quadrature output frequency and the clock signal in-phase output frequency being a fraction of the frequency of the single clock frequency. The PLL includes a single voltage controlled oscillator (VCO) that generates the single clock frequency. A plurality of dividers is included in the clock generator circuit and is responsive to the clock signal quadrature output frequency and the clock signal in-phase output frequency and generates multiple clock frequencies, each clock frequency being a unique frequency, each of the plurality of dividers generating an output, the final output of the plurality of dividers being synchronized to the reference frequency.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: November 26, 2013
    Assignee: Quintic Holdings
    Inventors: Yifeng Zhang, Peiqi Xuan, Kanyu Cao, Xiaodong Jin
  • Patent number: 8359074
    Abstract: A dummy circuit is provided to which a bias circuit of an low noise amplifier (LNA) can be coupled to during power down of the LNA. The dummy circuit maintains the bias circuit at an approximately normal operating state to reduce wake up time of the LNA.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: January 22, 2013
    Assignee: Marvell International Ltd.
    Inventors: Xiaodong Jin, King Chun Tsai, Yonghua Song
  • Patent number: 8258869
    Abstract: An LNA circuit for providing a wide range of gain while maintaining the output headroom. In a radio frequency (RF) receiver, the signal received by the receiver may be extremely small. For a transmitter in a short distance, the received signal may be relatively strong. A low power amplifier usually is used to amplify the input signal. The LNA has to be designed to accommodate a wide range of gain. A convention LNA circuit supporting a wide range of gain often suffers from reduced output headroom due to increased current through the load resistor. The present invention discloses the use of current bleeding branch to allow a portion of current to flow through the current bleeding branch and consequently reduces the current that would have flown through the load resistor. Consequently, the voltage across the load resistor may be maintained low to allow adequate output headroom.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: September 4, 2012
    Assignee: Quintic Holdings
    Inventors: Zhongwu Zhao, Xiaodong Jin
  • Publication number: 20120026407
    Abstract: A configurable multi-standard receiver. A receiver comprises a mixer, a processing module and an analog to digital converter is disclosed to receive multi-standard radio signals. The processing module includes a first selection switch and first parameter control, where the first selection switch configures the processing module as a complex filter or a real-valued filter and the first parameter control configures the characteristics of the filter. Furthermore, the analog to digital converted is preferably implemented using sigma delta modulation to achieve a desired noise shaping. The sigma delta modulation comprises a second selection switch and second parameter control. The second selection switch configures the sigma delta modulation to function as a unit having a complex loop filter or a unit having real-valued loop filters. The second parameter control configures the characteristics of the loop filter.
    Type: Application
    Filed: May 26, 2011
    Publication date: February 2, 2012
    Applicant: QUINTIC HOLDINGS
    Inventors: Yifeng Zhang, Rong Liu, Peiqi Xuan, Xiaodong Jin
  • Publication number: 20120025911
    Abstract: An LNA circuit for providing a wide range of gain while maintaining the output headroom. In a radio frequency (RF) receiver, the signal received by the receiver may be extremely small. For a transmitter in a short distance, the received signal may be relatively strong. A low power amplifier usually is used to amplify the input signal. The LNA has to be designed to accommodate a wide range of gain. A convention LNA circuit supporting a wide range of gain often suffers from reduced output headroom due to increased current through the load resistor. The present invention discloses the use of current bleeding branch to allow a portion of current to flow through the current bleeding branch and consequently reduces the current that would have flown through the load resistor. Consequently, the voltage across the load resistor may be maintained low to allow adequate output headroom.
    Type: Application
    Filed: September 30, 2010
    Publication date: February 2, 2012
    Applicant: QUINTIC HOLDINGS
    Inventors: Zhongwu Zhao, Xiaodong Jin
  • Patent number: 8031006
    Abstract: A low noise amplifier includes an input stage. The input stage includes a first device configured to receive an input signal. A second device is connected to the first device. The second device has a predetermined input impedance. The input stage is configured so that a change in the input signal to the first device causes a linearly proportional change in a conductance of the first device. A voltage at a junction between the first device and the second device remains substantially constant due to the predetermined input impedance of the second device.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: October 4, 2011
    Assignee: Marvell International Ltd.
    Inventors: Xiaodong Jin, Lawrence Tse, King Chun Tsai, George Chien
  • Patent number: 8027644
    Abstract: A transceiver system includes a first receive path with a first antenna configured to receive first signals, a first configuration switch, a first low noise amplifier configured to amplify the first signals, a second configuration switch, and a receiver. The first receive path is selectively configured to supply the amplified first signals to the receiver via the first antenna, the first configuration switch, the first low noise amplifier, and the second configuration switch. A second receive path includes a second antenna configured to receive second signals, a second low noise amplifier configured to amplify the second signals, the second configuration switch, and the receiver. The second receive path (i) includes fewer configuration switches than the first receive path and (ii) is selectively configured to supply the amplified second signals to the receiver via the second antenna, the second low noise amplifier, and the second configuration switch.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: September 27, 2011
    Assignee: Marvell International Ltd.
    Inventors: Xiaodong Jin, Sehat Sutardja, Lawrence Tse
  • Patent number: 8000067
    Abstract: An electrostatic discharge (ESD) circuit operable to protect an internal circuit from ESD events and protect the internal circuit from high-side supply noise.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: August 16, 2011
    Assignee: Marvell International Ltd.
    Inventors: Xiaodong Jin, Sehat Sutardja, Lawrence Tse, King Chun Tsai
  • Patent number: 7877075
    Abstract: A single-ended-to-differential mixer includes a differential input circuit having a single-ended input. The differential input circuit is responsive to a single-ended input signal to generate first and second signals. The single-ended-to-differential mixer includes a passive tank circuit in communication between a reference voltage and the differential input circuit. The single-ended-to-differential mixer includes a mixer circuit in communication with the differential input circuit and responsive to the first and second signals and a second input signal to generate a differential mixer output signal.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: January 25, 2011
    Assignee: Marvell International Ltd.
    Inventors: Xiaodong Jin, Lawrence Tse
  • Publication number: 20110003562
    Abstract: A transceiver system includes a first receive path with a first antenna configured to receive first signals, a first configuration switch, a first low noise amplifier configured to amplify the first signals, a second configuration switch, and a receiver. The first receive path is selectively configured to supply the amplified first signals to the receiver via the first antenna, the first configuration switch, the first low noise amplifier, and the second configuration switch. A second receive path includes a second antenna configured to receive second signals, a second low noise amplifier configured to amplify the second signals, the second configuration switch, and the receiver. The second receive path (i) includes fewer configuration switches than the first receive path and (ii) is selectively configured to supply the amplified second signals to the receiver via the second antenna, the second low noise amplifier, and the second configuration switch.
    Type: Application
    Filed: September 14, 2010
    Publication date: January 6, 2011
    Inventors: Xiaodong Jin, Sehat Sutardja, Lawrence Tse
  • Patent number: 7796952
    Abstract: A system for communicating information signals includes a receiver in selective communication with a first antenna and a second antenna. The receiver is configured to selectively receive information signals via the first or second antenna. The system includes a first low-noise amplifier in communication with the first antenna and in selective communication with the receiver. The first low-noise amplifier is configured to amplify a first information signal received by the first antenna to generate a first amplified signal. The system includes a second low-noise amplifier in communication with the second antenna and in selective communication with the receiver. At least the first and second low-noise amplifiers are formed on a monolithic substrate. The second low-noise amplifier is configured to amplify a second information signal received by the second antenna to generate a second amplified signal. Either the first or second amplified signal is selectively applied to the receiver.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: September 14, 2010
    Assignee: Marvell International Ltd.
    Inventors: Xiaodong Jin, Sehat Sutardja, Lawrence Tse
  • Patent number: 7751164
    Abstract: A method for reducing a parasitic capacitance of an electrostatic discharge (ESD) protection circuit for an integrated circuit (IC) includes providing an ESD protection circuit including a plurality of transistors; coupling one end of a resistor to a shared drain of the plurality of transistors; and coupling an opposite end of the resistor to at least one of an input pad of the IC, a blocking capacitor of the IC and a transistor in the IC.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: July 6, 2010
    Assignee: Marvell International Ltd.
    Inventors: Xiaodong Jin, Sehat Sutardja, Lawrence Tse, King Chun Tsai
  • Patent number: 7676212
    Abstract: A mixer comprises a differential input circuit that is configured to receive an input signal. The mixer comprises a tank circuit including a tuning capacitor arranged in parallel with an inductor. A resonant frequency of the inductor and tuning capacitor is substantially centered around a predetermined frequency of the input signal. The mixer comprises a mixer circuit that communicates with the differential input circuit and that is configured to receive first and second current signals and a second input signal. The mixer circuit is configured as a Gilbert cell double-balanced switching mixer for generating a differential mixer output signal as a product of the first and second current signals and the second input signal.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: March 9, 2010
    Assignee: Marvell International Ltd.
    Inventors: Xiaodong Jin, Lawrence Tse
  • Patent number: 7598814
    Abstract: A low noise amplifier (LNA) circuit includes a linear input stage including a first circuit that generates an output current and has a low input impedance. A device receives an input signal, communicates with the low impedance input of the first circuit, and includes a variable resistor having a resistance that varies based on the input signal.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: October 6, 2009
    Assignee: Marvell International Ltd.
    Inventors: Xiaodong Jin, Lawrence Tse, King Chun Tsai, George Chien
  • Publication number: 20090243690
    Abstract: In an embodiment of the present invention, a clock generator circuit is disclosed to include a phase locked loop (PLL) that is responsive to a clock signal quadrature output frequency and a clock signal in-phase output frequency. The clock generator circuit generates a single clock frequency that is a fraction of the frequency of the clock signal quadrature output frequency and the clock signal in-phase output frequency. The PLL includes a single voltage controlled oscillator (VCO) that generates the single clock frequency. A plurality of dividers is included in the clock generator circuit and is responsive to the clock signal quadrature output frequency and the clock signal in-phase output frequency and generates multiple clock frequencies, each clock frequency being a unique frequency, each of the plurality of dividers generating an output that is phase and frequency synchronized to the single clock frequency.
    Type: Application
    Filed: March 3, 2008
    Publication date: October 1, 2009
    Applicant: QUINTIC HOLDINGS
    Inventors: Yifeng ZHANG, Peiqi XUAN, Kanyu CAO, Xiaodong JIN