Patents by Inventor Xiaoju Wu

Xiaoju Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180269317
    Abstract: In at least some embodiments, a semiconductor device comprises a source region is formed within a well. The source region comprises a first dopant type, and the well comprises a second dopant type opposite the first dopant type. A termination region is formed within the well, the termination region being aligned with the source region and having an end adjacent to and spaced apart from an end of the source region. The termination region comprises a semiconducting material having the second dopant type. A preselected concentration value of the dopant in the termination region is greater than a concentration value of the second dopant type in the well.
    Type: Application
    Filed: May 24, 2018
    Publication date: September 20, 2018
    Inventor: Xiaoju Wu
  • Publication number: 20180197986
    Abstract: A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+ source and a second pwell is on an opposite side of the nwell finger including a p+ drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary.
    Type: Application
    Filed: March 8, 2018
    Publication date: July 12, 2018
    Inventors: CHIN-YU TSAI, IMRAN KHAN, XIAOJU WU
  • Publication number: 20180190813
    Abstract: In at least some embodiments, a semiconductor device comprises a source region is formed within a well. The source region comprises a first dopant type, and the well comprises a second dopant type opposite the first dopant type. A termination region is formed within the well, the termination region being aligned with the source region and having an end adjacent to and spaced apart from an end of the source region. The termination region comprises a semiconducting material having the second dopant type. A preselected concentration value of the dopant in the termination region is greater than a concentration value of the second dopant type in the well.
    Type: Application
    Filed: May 16, 2017
    Publication date: July 5, 2018
    Inventor: Xiaoju WU
  • Patent number: 10014405
    Abstract: In at least some embodiments, a semiconductor device comprises a source region is formed within a well. The source region comprises a first dopant type, and the well comprises a second dopant type opposite the first dopant type. A termination region is formed within the well, the termination region being aligned with the source region and having an end adjacent to and spaced apart from an end of the source region. The termination region comprises a semiconducting material having the second dopant type. A preselected concentration value of the dopant in the termination region is greater than a concentration value of the second dopant type in the well.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: July 3, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Xiaoju Wu
  • Publication number: 20180130798
    Abstract: An integrated circuit with transistor regions formed on a substrate. Each transistor region includes a channel region and a terminal region. The channel region is positioned along a traverse dimension, and it includes a channel edge region along a longitudinal dimension. The terminal region is positioned adjacent to the channel region, and it is doped with a first dopant of a first conductivity type. Each transistor region may include an edge block region, which is positioned along the longitudinal dimension and adjacent to the channel edge region. The edge block region is doped with a second dopant of a second conductivity type opposite to the first conductivity type. The channel region doped with a dopant and having a first doping concentration. Each transistor region may include an edge recovery region overlapping with the channel edge region and having a second doping concentration higher than the first doping concentration.
    Type: Application
    Filed: January 9, 2018
    Publication date: May 10, 2018
    Inventors: Xiaoju Wu, C. Matthew Thompson
  • Patent number: 9947783
    Abstract: A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+ source and a second pwell is on an opposite side of the nwell finger including a p+ drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: April 17, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chin-Yu Tsai, Imran Khan, Xiaoju Wu
  • Patent number: 9899376
    Abstract: An integrated circuit with transistor regions formed on a substrate. Each transistor region includes a channel region and a terminal region. The channel region is positioned along a traverse dimension, and it includes a channel edge region along a longitudinal dimension. The terminal region is positioned adjacent to the channel region, and it is doped with a first dopant of a first conductivity type. Each transistor region may include an edge block region, which is positioned along the longitudinal dimension and adjacent to the channel edge region. The edge block region is doped with a second dopant of a second conductivity type opposite to the first conductivity type. The channel region doped with a dopant and having a first doping concentration. Each transistor region may include an edge recovery region overlapping with the channel edge region and having a second doping concentration higher than the first doping concentration.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: February 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiaoju Wu, C. Matthew Thompson
  • Publication number: 20170309744
    Abstract: A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+source and a second pwell is on an opposite side of the nwell finger including a p+drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary.
    Type: Application
    Filed: April 21, 2016
    Publication date: October 26, 2017
    Inventors: CHIN-YU TSAI, IMRAN KHAN, XIAOJU WU
  • Publication number: 20170257088
    Abstract: An interface device includes an NPN structure along a horizontal surface of a p-doped substrate. The NPN structure has a first n-doped region coupled to an output terminal, a p-doped region surrounding the first n-doped region and coupled to the output terminal, and a second n-doped region separated from the first n-doped region by the p-doped region. The interface device also includes a PNP structure along a vertical depth of the p-doped substrate. The PNP structure includes the p-doped region, an n-doped layer under the p-doped region, and the p-doped substrate. Advantageously, the interface device can withstand high voltage swing (both positive and negative), prevent sinking and sourcing large load current, and avoid entering into a low resistance mode during power down operations.
    Type: Application
    Filed: December 21, 2016
    Publication date: September 7, 2017
    Inventors: Xiaoju Wu, Rajesh Keloth, Sudheer Prasad
  • Publication number: 20170256537
    Abstract: An integrated circuit with transistor regions formed on a substrate. Each transistor region includes a channel region and a terminal region. The channel region is positioned along a traverse dimension, and it includes a channel edge region along a longitudinal dimension. The terminal region is positioned adjacent to the channel region, and it is doped with a first dopant of a first conductivity type. Each transistor region may include an edge block region, which is positioned along the longitudinal dimension and adjacent to the channel edge region. The edge block region is doped with a second dopant of a second conductivity type opposite to the first conductivity type. The channel region doped with a dopant and having a first doping concentration. Each transistor region may include an edge recovery region overlapping with the channel edge region and having a second doping concentration higher than the first doping concentration.
    Type: Application
    Filed: March 4, 2016
    Publication date: September 7, 2017
    Inventors: Xiaoju Wu, C. Matthew Thompson
  • Patent number: 9221039
    Abstract: Disclosed herein are a catalyst, a preparation process thereof, and a process of epoxidizing olefin using the catalyst. The catalyst contains a binder and a titanium silicate as specified. The catalyst disclosed herein has high strength, and shows high catalytic activity in the epoxidation of olefins.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: December 29, 2015
    Assignees: China Petroleum & Chemical Corporation, Hunan Changling Petrochemical Science and Technology Development Co., Ltd., Research Institute of Petroleum Processing, Sinopec
    Inventors: Min Lin, Hua Li, Wei Wang, Chijian He, Xiaoju Wu, Jizao Gao, Xichun She, Jun Long, Qingling Chen
  • Publication number: 20150294967
    Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.
    Type: Application
    Filed: June 25, 2015
    Publication date: October 15, 2015
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
  • Patent number: 9099523
    Abstract: A semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the buried layer. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the buried layer.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: August 4, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
  • Patent number: 8859791
    Abstract: A process for producing an alkylene oxide by olefin epoxidation, wherein said process comprises the steps of: (1) in a first olefin epoxidation condition, in the presence of a first solid catalyst, a first mixed stream containing a solvent, an olefin and H2O2 is subjected to an epoxidation in one or more fixed bed reactors and/or one or more moving bed reactors until the conversion of H2O2 reaches 50%-95%, then, optionally, the resulting reaction mixture obtained in the step (1) is subjected to a separation to obtain a first stream free of H2O2 and a second stream containing the unreacted H2O2, and the olefin is introduced to the second stream to produce a second mixed stream, or optionally, the olefin is introduced to the reaction mixture obtained in the step (1) to produce a second mixed stream; (2) in a second olefin epoxidation condition, the reaction mixture obtained in the step (1) or the second mixed stream obtained in the step (1) and a second solid catalyst are introduced to one or more slurry bed re
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: October 14, 2014
    Assignees: China Petroleum & Chemical Corporation, Hunan Changling Petrochemical Science and Technology Development Co. Ltd., Research Institute of Petroleum Processing, Sinopec
    Inventors: Hua Li, Min Lin, Xiaoju Wu, Wei Wang, Chijian He, Jizao Gao, Xingtian Shu, Shuanghua Wan, Bin Zhu
  • Publication number: 20140124828
    Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
  • Patent number: 8581324
    Abstract: Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: November 12, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Xiaoju Wu, Jozef Czeslaw Mitros
  • Publication number: 20130253208
    Abstract: The present invention provides a catalyst and the preparation process thereof and a process of epoxidising olefin using the catalyst. The catalyst contains a binder and a titanium silicate, the binder being an amorphous silica, the titanium silicate having a MFI structure, and the crystal grain of the titanium silicate having a hollow structure, with a radial length of 5-300 nm for the cavity portion of the hollow structure, wherein the adsorption capacity of benzene measured for the titanium silicate under the conditions of 25 degrees C., P/P0=0.
    Type: Application
    Filed: October 11, 2011
    Publication date: September 26, 2013
    Applicants: CHINA PETROLEUM & CHEMICAL CORPORATION, Research Institute of Petroleum Processing, Sinope Sinopec, Hunan Changling Pertrochemical Science and Technology Development Co. Ltd.
    Inventors: Min Lin, Hua Li, Wei Wang, Chijian He, Xiaoju Wu, Jizao Gao, Xichun She, Jun Long, Qingling Chen
  • Publication number: 20130211112
    Abstract: A process for producing an alkylene oxide by olefin epoxidation, wherein said process comprises the steps of: (1) in a first olefin epoxidation condition, in the presence of a first solid catalyst, a first mixed stream containing a solvent, an olefin and H2O2 is subjected to an epoxidation in one or more fixed bed reactors and/or one or more moving bed reactors until the conversion of H2O2 reaches 50%-95%, then, optionally, the resulting reaction mixture obtained in the step (1) is subjected to a separation to obtain a first stream free of H2O2 and a second stream containing the unreacted H2O2, and the olefin is introduced to the second stream to produce a second mixed stream, or optionally, the olefin is introduced to the reaction mixture obtained in the step (1) to produce a second mixed stream; (2) in a second olefin epoxidation condition, the reaction mixture obtained in the step (1) or the second mixed stream obtained in the step (1) and a second solid catalyst are introduced to one or more slurry bed re
    Type: Application
    Filed: October 11, 2011
    Publication date: August 15, 2013
    Applicant: CHINA PETROLEUM & CHEMICAL CORPORATION
    Inventors: Hua Li, Min Lin, Xiaoju Wu, Wei Wang, Chijian He, Jizao Gao, Xingtian Shu, Shuanghua Wan, Bin Zhu
  • Publication number: 20120074479
    Abstract: Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.
    Type: Application
    Filed: December 6, 2011
    Publication date: March 29, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiaoju Wu, Jozef Czeslaw Mitros
  • Patent number: 8125830
    Abstract: Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: February 28, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Xiaoju Wu, Jozef Czeslaw Mitros