Patents by Inventor Xiaoju Wu

Xiaoju Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7348228
    Abstract: A junction field effect transistor (JFET) is fashioned where a channel of transistor is buried deeply within the workpiece within which the JFET is formed. Burying the channel below the surface of the workpiece and/or away from overlying conductive materials distances a current that flows in the channel from outside influences, such as the effects of the overlying conductive materials. The deep channel also provides a more regular path for the current flowing therein by moving the channel away from non-uniformities on or near the surface of the workpiece, where said non-uniformities or irregularities would interrupt or otherwise disturb current flowing in a channel that is not as deep. These aspects of the deep channel serve to reduce noise and allow the transistor to operate in a more repeatable and predictable manner, among other things.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: March 25, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Xiaoju Wu
  • Patent number: 7307309
    Abstract: A method forming a current path in a substrate (322) having a first conductivity type is disclosed. The method includes forming an impurity region (314) having a second conductivity type and extending from a face of the substrate to a first depth. A hole (305) is formed in the impurity region. A first dielectric layer (360-364) is formed on an inner surface of the hole. A first electrode (306) is formed in the hole adjacent the dielectric layer.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: December 11, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Jozef Mitros, Xiaoju Wu
  • Publication number: 20070275515
    Abstract: A junction field effect transistor (JFET) is fashioned where a channel of transistor is buried deeply within the workpiece within which the JFET is formed. Burying the channel below the surface of the workpiece and/or away from overlying conductive materials distances a current that flows in the channel from outside influences, such as the effects of the overlying conductive materials. The deep channel also provides a more regular path for the current flowing therein by moving the channel away from non-uniformities on or near the surface of the workpiece, where said non-uniformities or irregularities would interrupt or otherwise disturb current flowing in a channel that is not as deep. These aspects of the deep channel serve to reduce noise and allow the transistor to operate in a more repeatable and predictable manner, among other things.
    Type: Application
    Filed: May 25, 2006
    Publication date: November 29, 2007
    Inventor: Xiaoju Wu
  • Publication number: 20070164366
    Abstract: Excessive thinning of a thin oxide in a dual gate CMOS fabrication process is mitigated. A thick gate oxide utilized to form high voltage transistors is selectively patterned to leave some thick oxide in an active area where low voltage transistors are formed. Due to fabrication conditions, the thin gate oxide that is formed in an active area where the low voltage transistors are formed may become too thin, particularly in perimeter areas of the low voltage area. Accordingly, the thick gate oxide is patterned so that some of it remains in perimeter areas of the low voltage active area. This mitigates leakage and/or other unwanted conditions that may result if low voltage transistors are formed using the gate oxide that is too thin.
    Type: Application
    Filed: January 13, 2006
    Publication date: July 19, 2007
    Inventors: Xiaoju Wu, Victor Ivanov, Khan Imran
  • Patent number: 7244651
    Abstract: The leakage current of an OTP-EPROM cell formed using buried channel PMOS technology can be reduced. The reduction in leakage current of the OTP-EPROM can be achieved by blocking implantation of the Vtp implant into a channel region of an n-well that substantially underlies a floating gate structure. The Vtp implant can be blocked by providing a mask overlying the surface of the channel region of the n-well during implantation of the Vtp implant.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: July 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Xiaoju Wu, Jozef Mitros, Pinghai Hao
  • Publication number: 20070080400
    Abstract: We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over the buried layer contacting gate regions that connect to a gate terminal. The channel region, of which the length spans the distance between the buried layer and a source region, is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.
    Type: Application
    Filed: December 12, 2006
    Publication date: April 12, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Pendharker, Pinghai Hao, Xiaoju Wu
  • Patent number: 7164160
    Abstract: We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over the buried layer contacting gate regions that connect to a gate terminal. The channel region, of which the length spans the distance between the buried layer and a source region, is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: January 16, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer P. Pendharker, Pinghai Hao, Xiaoju Wu
  • Publication number: 20060262599
    Abstract: An electrically erasable programmable read only memory (EEPROM) (500) is disclosed having improved data retention and read/write endurance. The EEPROM also lacks a more conventional cross coupling arrangement and thus is more area efficient than conventional EEPROM cells. The EEPROM (500) includes a PMOS transistor portion (514a) and an NMOS transistor portion (514b), where respective currents of these devices are compared to one another (e.g., subtracted) to give a differential reading that provides for the state of the EEPROM (500).
    Type: Application
    Filed: May 18, 2005
    Publication date: November 23, 2006
    Inventor: Xiaoju Wu
  • Publication number: 20060244036
    Abstract: The formation of a one time programmable (OTP) transistor based electrically programmable read only memory (EPROM) cell (100) is disclosed. The cell (100) includes multiple concentric rings (108, 110) out of which gate structures are formed. An inner transistor based cell (130) formed from the inner ring (108) is shielded from isolation material (106) by one or more outer rings (110). The lack of overlap between the inner transistor and any isolation material promotes enhanced charge/data retention by mitigating high electric fields that may develop at such overlap regions (30, 32).
    Type: Application
    Filed: April 29, 2005
    Publication date: November 2, 2006
    Inventor: Xiaoju Wu
  • Patent number: 7112953
    Abstract: The present invention provides a method for monitoring a shift in a buried layer in a semiconductor device. The method for monitoring the shift in the buried layer, among other steps, includes forming a buried layer test structure in, on or over a substrate of a semiconductor device, the buried layer test structure including a first test buried layer located in or on the substrate, the first test buried layer shifted a predetermined distance with respect to a first test feature. The buried layer test structure further includes a second test buried layer lodated in the substrate, the second test buried layer shifted a predetermined but different distance with respect to a second test feature. The method for monitoring the shift in the buried layer may further include applying a test signal to the buried layer test structure to determine an actual shift relative to the predetermined shift.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: September 26, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Xinfen Chen, Xiaoju Wu, John K. Arch, Qingfeng Wang
  • Patent number: 7018880
    Abstract: The present invention provides, in one embodiment, a method of reducing 1/f noise in a metal oxide semiconductor (MOS) device (100). The method comprises forming an oxide layer (110) on a silicon substrate (105) and depositing a polysilicon layer (115) on the oxide layer (110). The method further includes implanting a fluorine dopant (130) into the polysilicon layer (115) at an implant dose of at least about 4×1014 atoms/cm2. The polysilicon layer (115) is thermally annealed such that a portion of the fluorine dopant (130) is diffused into the oxide layer (110) to thereby reduce a 1/f noise of the MOS device (100). Other embodiments of the provide a MOS device (300) manufactured by the above-described method and a method of manufacturing an integrated circuit (500) that includes the above-described method.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: March 28, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Larry B. Anderson, Fan Chi Hou, Xiaoju Wu, Yvonne Patton, Shanjen Pan, Zafar Imam
  • Publication number: 20060038553
    Abstract: The present invention provides a method for monitoring a shift in a buried layer in a semiconductor device and a method for manufacturing an integrated circuit using the method for monitoring the shift in the buried layer. The method for monitoring the shift in the buried layer, among other steps, includes forming a buried layer test structure (200) in, on or over a substrate (210) of a semiconductor device, the buried layer test structure (200) including a first test buried layer (230a) located in or on the substrate (210), the first test buried layer (230a) shifted a predetermined distance with respect to a first test feature (240a). The buried layer test structure (200) further includes a second test buried layer (230b) located in the substrate (210), the second test buried layer (23b) shifted a predetermined but different distance with respect to a second test feature (240b).
    Type: Application
    Filed: February 2, 2005
    Publication date: February 23, 2006
    Applicant: Texas Instruments, Inc.
    Inventors: Xinfen Chen, Xiaoju Wu, John Arch, Qingfeng Wang
  • Publication number: 20050194631
    Abstract: A method forming a current path in a substrate (322) having a first conductivity type is disclosed. The method includes forming an impurity region (314) having a second conductivity type and extending from a face of the substrate to a first depth. A hole (305) is formed in the impurity region. A first dielectric layer (360-364) is formed on an inner surface of the hole. A first electrode (306) is formed in the hole adjacent the dielectric layer.
    Type: Application
    Filed: March 4, 2004
    Publication date: September 8, 2005
    Inventors: Pinghai Hao, Jozef Mitros, Xiaoju Wu
  • Patent number: 6921701
    Abstract: A method of forming a semiconductor device includes forming a body region of a semiconductor substrate and forming a drift region adjacent at least a portion of the body region. A dopant is used to form the drift region. The dopant may comprise phosphorous. The method also includes forming a field oxide structure adjacent a portion of the drift region and a portion of a drain region. The field oxide structure is located between a gate electrode region and the drain region and is spaced apart from the gate electrode region. Atoms of the dopant accumulate adjacent a portion of the field oxide structure, forming an intermediate-doped region adjacent a portion of the field oxide structure. The method includes forming a gate oxide adjacent a portion of the body region and forming a gate electrode adjacent a portion of the gate oxide.
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: July 26, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Xiaoju Wu
  • Publication number: 20050136579
    Abstract: The present invention provides, in one embodiment, a method of reducing 1/f noise in a metal oxide semiconductor (MOS) device (100). The method comprises forming an oxide layer (110) on a silicon substrate (105) and depositing a polysilicon layer (115) on the oxide layer (110). The method further includes implanting a fluorine dopant (130) into the polysilicon layer (115) at an implant dose of at least about 4×1014 atoms/cm2. The polysilicon layer (115) is thermally annealed such that a portion of the fluorine dopant (130) is diffused into the oxide layer (110) to thereby reduce a 1/f noise of the MOS device (100). Other embodiments of the provide a MOS device (300) manufactured by the above-described method and a method of manufacturing an integrated circuit (500) that includes the above-described method.
    Type: Application
    Filed: December 22, 2003
    Publication date: June 23, 2005
    Applicant: Texas Instruments, Incorporated
    Inventors: Pinghai Hao, Larry Anderson, Fan Chi Hou, Xiaoju Wu, Yvonne Patton, Shanjen Pan, Zafar Imam
  • Patent number: 6885054
    Abstract: The present invention provides a threshold voltage stabilizer for use with a MOS transistor having a body effect associated therewith. In one embodiment, the threshold voltage stabilizer, includes a body well located in a substrate, a source located in the body well, and a stabilization region positioned below the body well. The threshold voltage stabilizer is configured to provide a stabilization voltage to the stabilization region to increase a depletion region within the body well and thereby restrict the body effect to stabilize a threshold voltage of the MOS transistor.
    Type: Grant
    Filed: February 4, 2004
    Date of Patent: April 26, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Xiaoju Wu, Pinghai Hao, Imran M. Khan
  • Publication number: 20050067631
    Abstract: We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over the buried layer contacting gate regions that connect to a gate terminal. The channel region, of which the length spans the distance between the buried layer and a source region, is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.
    Type: Application
    Filed: September 29, 2003
    Publication date: March 31, 2005
    Inventors: Sameer Pendharker, Pinghai Hao, Xiaoju Wu
  • Patent number: 6870242
    Abstract: A method including a buried layer formed on a semiconductor substrate, an active region formed adjacent to at least a portion of the buried layer, an isolation structure formed adjacent to at least a portion of the active region, and a gate oxide formed adjacent to at least a portion of the active region. The method also includes a polysilicon layer formed adjacent to at least a portion of the gate oxide having a portion removed to form a polysilicon definition structure that substantially surrounds and defines an emitter contact region. The method also includes forming a self-aligned implant region of the emitter contact region.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: March 22, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Xiaoju Wu
  • Publication number: 20040235246
    Abstract: The leakage current of an OTP-EPROM cell formed using buried channel PMOS technology can be reduced. The reduction in leakage current of the OTP-EPROM can be achieved by blocking implantation of the Vtp implant into a channel region of an n-well that substantially underlies a floating gate structure. The Vtp implant can be blocked by providing a mask overlying the surface of the channel region of the n-well during implantation of the Vtp implant.
    Type: Application
    Filed: May 21, 2003
    Publication date: November 25, 2004
    Inventors: Xiaoju Wu, Jozef Mitros, Pinghai Hao
  • Patent number: 6790736
    Abstract: In accordance with a particular embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer, and an isolation structure is formed adjacent at least a portion of the active region. A gate oxide is formed adjacent at least a portion of the active region. The method also includes forming a polysilicon layer adjacent at least a portion of the gate oxide. At least a portion of the polysilicon layer is removed to form a polysilicon definition structure. The polysilicon definition structure at least substantially surrounds and defines an emitter contact region. The method also includes forming an implant region of the emitter contact region, wherein the implant region is self-aligned.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: September 14, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Xiaoju Wu