Patents by Inventor Xiaoju Wu

Xiaoju Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040175892
    Abstract: A method of forming a semiconductor device includes forming a body region of a semiconductor substrate and forming a drift region adjacent at least a portion of the body region. A dopant is used to form the drift region. The dopant may comprise phosphorous. The method also includes forming a field oxide structure adjacent a portion of the drift region and a portion of a drain region. The field oxide structure is located between a gate electrode region and the drain region and is spaced apart from the gate electrode region. Atoms of the dopant accumulate adjacent a portion of the field oxide structure, forming an intermediate-doped region adjacent a portion of the field oxide structure. The method includes forming a gate oxide adjacent a portion of the body region and forming a gate electrode adjacent a portion of the gate oxide.
    Type: Application
    Filed: March 15, 2004
    Publication date: September 9, 2004
    Inventor: Xiaoju Wu
  • Patent number: 6730962
    Abstract: A method of forming a semiconductor device includes forming a body region of a semiconductor substrate and forming a drift region adjacent at least a portion of the body region. A dopant is used to form the drift region. The dopant may comprise phosphorous. The method also includes forming a field oxide structure adjacent a portion of the drift region and a portion of a drain region. The field oxide structure is located between a gate electrode region and the drain region and is spaced apart from the gate electrode region. Atoms of the dopant accumulate adjacent a portion of the field oxide structure, forming an intermediate-doped region adjacent a portion of the field oxide structure. The method includes forming a gate oxide adjacent a portion of the body region and forming a gate electrode adjacent a portion of the gate oxide.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: May 4, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Xiaoju Wu
  • Publication number: 20040058505
    Abstract: In accordance with a particular embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer, and an isolation structure is formed adjacent at least a portion of the active region. A gate oxide is formed adjacent at least a portion of the active region. The method also includes forming a polysilicon layer adjacent at least a portion of the gate oxide. At least a portion of the polysilicon layer is removed to form a polysilicon definition structure. The polysilicon definition structure at least substantially surrounds and defines an emitter contact region. The method also includes forming an implant region of the emitter contact region, wherein the implant region is self-aligned.
    Type: Application
    Filed: September 19, 2003
    Publication date: March 25, 2004
    Inventor: Xiaoju Wu
  • Publication number: 20030141537
    Abstract: The present invention provides a system for efficiently producing versatile multiple input floating gate structures. The present invention provides multiple-input floating gate device (100, 400) that has a first input (106, 406) formed in a first active device region (202, 502) and a second input (108, 408) formed in a second active device region (204, 504). A floating gate (200, 500) is disposed upon the first and second inputs, separated from the inputs by a dielectric layer. A device body, formed in a third active device region (210, 506), is coupled to the first and second inputs through the floating gate.
    Type: Application
    Filed: December 17, 2002
    Publication date: July 31, 2003
    Inventor: Xiaoju Wu
  • Publication number: 20030109112
    Abstract: A method of forming a semiconductor device includes forming a body region of a semiconductor substrate and forming a drift region adjacent at least a portion of the body region. A dopant is used to form the drift region. The dopant may comprise phosphorous. The method also includes forming a field oxide structure adjacent a portion of the drift region and a portion of a drain region. The field oxide structure is located between a gate electrode region and the drain region and is spaced apart from the gate electrode region. Atoms of the dopant accumulate adjacent a portion of the field oxide structure, forming an intermediate-doped region adjacent a portion of the field oxide structure. The method includes forming a gate oxide adjacent a portion of the body region and forming a gate electrode adjacent a portion of the gate oxide.
    Type: Application
    Filed: December 7, 2001
    Publication date: June 12, 2003
    Applicant: Texas Instruments Incorporated
    Inventor: Xiaoju Wu
  • Publication number: 20030100149
    Abstract: In accordance with a particular embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer, and an isolation structure is formed adjacent at least a portion of the active region. A gate oxide is formed adjacent at least a portion of the active region. The method also includes forming a polysilicon layer adjacent at least a portion of the gate oxide. At least a portion of the polysilicon layer is removed to form a polysilicon definition structure. The polysilicon definition structure at least substantially surrounds and defines an emitter contact region. The method also includes forming an implant region of the emitter contact region, wherein the implant region is self-aligned.
    Type: Application
    Filed: November 29, 2001
    Publication date: May 29, 2003
    Applicant: Texas Instruments Incorporated
    Inventor: Xiaoju Wu
  • Publication number: 20020149067
    Abstract: The present invention relates to an NMOS transistor structure which comprises a p-well region in a semiconductor substrate, an n-type source region in the p-well region, and an n-type drain region in the p-well region. The source and drain regions are laterally spaced apart from one another and define a p-type channel region therebetween in the p-well region. The NMOS transistor further comprises a gate having a gate electrode and a gate oxide overlying the channel region of the p-well region. A PDUF region underlies the p-well region and exhibits a resistivity which is less than the p-well region, wherein the PDUF region lowers a resistance associated with the p-well region at high drain voltages. The lowered resistance decreases a gain associated with a parasitic bipolar transistor and increases an injection induced breakdown voltage characteristic of the NMOS transistor structure.
    Type: Application
    Filed: April 12, 2001
    Publication date: October 17, 2002
    Inventors: Jozef C. Mitros, James R. Todd, Xiaoju Wu
  • Publication number: 20020084479
    Abstract: Capacitor area is increased in the vertical direction by forming capacitors on topographic features on the chip. The features are formed during existing process steps. Adding vertical topography increases capacitance per unit area, reducing die size at no added development cost or mask steps.
    Type: Application
    Filed: November 30, 2001
    Publication date: July 4, 2002
    Inventors: Shanjen Pan, Xiaoju Wu, Peter Ying
  • Publication number: 20020079530
    Abstract: An electronic circuit (20), comprising a semiconductor substrate (22) and a first layer (30) in a fixed physical relation to the semiconductor substrate. The electronic circuit further comprises a well (32a) formed in the first layer, wherein the well comprises a first conductivity type and has a side dimension and a bottom dimension. The electronic circuit further comprises a first enclosure (34, 26) surrounding the side dimension and the bottom dimension of the well, wherein the first enclosure comprises a second conductivity type complementary of the first conductivity type and has a side dimension and a bottom dimension. The electronic circuit further comprises a second enclosure (32b, 24) surrounding the side dimension and the bottom dimension of the first enclosure, wherein the second enclosure comprises the first conductivity type.
    Type: Application
    Filed: December 14, 2001
    Publication date: June 27, 2002
    Inventors: Xiaoju Wu, Pinhai Hao, Imran Khan, Jozef C. Mitros, James R. Todd, Robert Pan