Patents by Inventor Xiaolong Fang
Xiaolong Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230089141Abstract: Self-mixing interferometry (SMI) sensors may include vertical cavity surface emitting lasers (VCSEL), photodetectors, and microelectromechanical systems (MEMS). The VCSEL, photodetectors, and MEMS may be vertically stacked. The MEMS may be moveable with respect to a VCSEL and may change a cavity length associated with the VCSEL. By changing the cavity length associated with the VCSEL, certain properties of emitted light may be changed, such as a wavelength value of the emitted light.Type: ApplicationFiled: September 21, 2021Publication date: March 23, 2023Inventors: Tong Chen, Ahmet Fatih Cihan, Edward Vail, Weiping Li, Xiaolong Fang, Xibin Zhou, Pengfei Qiao
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Patent number: 11418010Abstract: An optoelectronic device includes a semiconductor substrate. A first set of thin-film layers is disposed on the substrate and defines a lower distributed Bragg-reflector (DBR) stack. A second set of thin-film layers is disposed over the lower DBR stack and defines an optical emission region, which is contained in a mesa defined by multiple trenches, which are disposed around the optical emission region without fully surrounding the optical emission region. A third set of thin-film layers is disposed over the optical emission region and defines an upper DBR stack. Electrodes are disposed around the mesa in gaps between the trenches and are configured to apply an excitation current to the optical emission region.Type: GrantFiled: March 9, 2020Date of Patent: August 16, 2022Assignee: APPLE INC.Inventors: Weiping Li, Arnaud Laflaquière, Xiaolong Fang
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Patent number: 11322630Abstract: An optoelectronic device includes a semiconductor substrate and a first stack of epitaxial layers, which are disposed over the semiconductor substrate and are configured to function as a photodetector, which emits a photocurrent in response to infrared radiation in a range of wavelengths greater than 940 nm. A second stack of epitaxial layers is disposed over the first stack and configured to function as an optical transmitter with an emission wavelength in the range of wavelengths greater than 940 nm.Type: GrantFiled: September 3, 2020Date of Patent: May 3, 2022Assignee: APPLE INC.Inventors: Weiping Li, Arnaud Laflaquière, Chinhan Lin, Fei Tan, Tong Chen, Xiaolong Fang
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Publication number: 20210091244Abstract: An optoelectronic device includes a semiconductor substrate and a first stack of epitaxial layers, which are disposed over the semiconductor substrate and are configured to function as a photodetector, which emits a photocurrent in response to infrared radiation in a range of wavelengths greater than 940 nm. A second stack of epitaxial layers is disposed over the first stack and configured to function as an optical transmitter with an emission wavelength in the range of wavelengths greater than 940 nm.Type: ApplicationFiled: September 3, 2020Publication date: March 25, 2021Inventors: Weiping Li, Arnaud Laflaquière, Chinhan Lin, Fei Tan, Tong Chen, Xiaolong Fang
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Publication number: 20200313391Abstract: An optoelectronic device includes a semiconductor substrate. A first set of thin-film layers is disposed on the substrate and defines a lower distributed Bragg-reflector (DBR) stack. A second set of thin-film layers is disposed over the lower DBR stack and defines an optical emission region, which is contained in a mesa defined by multiple trenches, which are disposed around the optical emission region without fully surrounding the optical emission region. A third set of thin-film layers is disposed over the optical emission region and defines an upper DBR stack. Electrodes are disposed around the mesa in gaps between the trenches and are configured to apply an excitation current to the optical emission region.Type: ApplicationFiled: March 9, 2020Publication date: October 1, 2020Inventors: Weiping Li, Arnaud Laflaquière, Xiaolong Fang
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Patent number: 9385278Abstract: Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor devices includes forming spaced-apart structures at a dicing street located between neighboring device growth regions of a substrate material. The method can further include epitaxially growing a semiconductor material by adding a first portion of semiconductor material to the device growth regions and adding a second portion of semiconductor material to the structures. The method can still further include forming semiconductor devices at the device growth regions, and separating the semiconductor devices from each other at the dicing street by removing the spaced-apart structures and the underlying substrate material at the dicing street.Type: GrantFiled: February 9, 2015Date of Patent: July 5, 2016Assignee: Micron Technology, Inc.Inventors: Xiaolong Fang, Lifang Xu, Tingkai Li, Thomas Gehrke
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Publication number: 20150155440Abstract: Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor devices includes forming spaced-apart structures at a dicing street located between neighboring device growth regions of a substrate material. The method can further include epitaxially growing a semiconductor material by adding a first portion of semiconductor material to the device growth regions and adding a second portion of semiconductor material to the structures. The method can still further include forming semiconductor devices at the device growth regions, and separating the semiconductor devices from each other at the dicing street by removing the spaced-apart structures and the underlying substrate material at the dicing street.Type: ApplicationFiled: February 9, 2015Publication date: June 4, 2015Inventors: Xiaolong Fang, Lifang Xu, Tingkai Li, Thomas Gehrke
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Patent number: 8980752Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.Type: GrantFiled: July 22, 2013Date of Patent: March 17, 2015Assignee: Micron Technology, Inc.Inventors: Farrell Good, Baosuo Zhou, Xiaolong Fang, Fatma Arzum Simsek-Ege
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Patent number: 8951842Abstract: Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor devices includes forming spaced-apart structures at a dicing street located between neighboring device growth regions of a substrate material. The method can further include epitaxially growing a semiconductor material by adding a first portion of semiconductor material to the device growth regions and adding a second portion of semiconductor material to the structures. The method can still further include forming semiconductor devices at the device growth regions, and separating the semiconductor devices from each other at the dicing street by removing the spaced-apart structures and the underlying substrate material at the dicing street.Type: GrantFiled: January 12, 2012Date of Patent: February 10, 2015Assignee: Micron Technology, Inc.Inventors: Xiaolong Fang, Lifang Xu, Tingkai Li, Thomas Gehrke
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Publication number: 20130309858Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.Type: ApplicationFiled: July 22, 2013Publication date: November 21, 2013Applicant: Micron Technology, Inc.Inventors: Farrell Good, Baosuo Zhou, Xiaolong Fang, Fatma Arzum Simsek-Ege
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Patent number: 8546888Abstract: Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first dielectric layer adjoining exposed substrate surfaces within the trench using a high-density plasma process, forming a layer of spin-on dielectric material on the first dielectric layer so as to fill a remaining portion of the trench, and densifying the layer of spin-on dielectric material.Type: GrantFiled: June 20, 2011Date of Patent: October 1, 2013Assignee: Micron Technology, Inc.Inventors: Zailong Bian, Xiaolong Fang
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Patent number: 8492278Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.Type: GrantFiled: March 30, 2010Date of Patent: July 23, 2013Assignee: Micron Technology, Inc.Inventors: Farrell Good, Baosuo Zhou, Xiaolong Fang, Fatma Arzum Simsek-Ege
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Publication number: 20130181219Abstract: Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor devices includes forming spaced-apart structures at a dicing street located between neighboring device growth regions of a substrate material. The method can further include epitaxially growing a semiconductor material by adding a first portion of semiconductor material to the device growth regions and adding a second portion of semiconductor material to the structures. The method can still further include forming semiconductor devices at the device growth regions, and separating the semiconductor devices from each other at the dicing street by removing the spaced-apart structures and the underlying substrate material at the dicing street.Type: ApplicationFiled: January 12, 2012Publication date: July 18, 2013Inventors: Xiaolong Fang, Lifang Xu, Tingkai Li, Thomas Gehrke
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Patent number: 8143167Abstract: Trench isolation structures and methods to form same for use in the manufacture of semiconductor devices are described. The trench isolation structures are formed using several processing schemes that utilize disclosed dry etching processes to form a significant depth ? between an array trench depth and a periphery trench depth. One etching method creates a trench delta depth utilizing a single dry etch step, while two other etching methods create a trench ? depth by utilizing three dry etch steps.Type: GrantFiled: March 3, 2009Date of Patent: March 27, 2012Assignee: Micron Technology, Inc.Inventors: Xiaolong Fang, Ramakanth Alapati, Tuman E. Allen
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Patent number: 8120137Abstract: Among structures, methods, devices, and systems for isolation trenches, a semiconductor device is provided that includes a substrate and an isolation trench structure. One such isolation trench structure includes a first isolation trench portion associated with a surface of the substrate and having a first pair of opposing sidewalls that are each substantially perpendicular to the surface of the substrate. A second isolation trench portion includes a second pair of sidewalls within the substrate that are each angled obliquely with respect to the surface of the substrate, where the second isolation trench portion has a separation between the second pair of sidewalls that decreases as a distance from the first isolation trench portion increases. A third isolation trench portion includes a third pair of sidewalls within the substrate that are each substantially perpendicular to the surface of the substrate.Type: GrantFiled: May 8, 2008Date of Patent: February 21, 2012Assignee: Micron Technology, Inc.Inventors: Michael A. Smith, Xiaolong Fang
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Publication number: 20110244674Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.Type: ApplicationFiled: March 30, 2010Publication date: October 6, 2011Inventors: Farrell Good, Baosuo Zhou, Xiaolong Fang, Fatma Arzum Simsek-Ege
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Publication number: 20110241096Abstract: Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first dielectric layer adjoining exposed substrate surfaces within the trench using a high-density plasma process, forming a layer of spin-on dielectric material on the first dielectric layer so as to fill a remaining portion of the trench, and densifying the layer of spin-on dielectric material.Type: ApplicationFiled: June 20, 2011Publication date: October 6, 2011Inventors: Zailong Bian, Xiaolong Fang
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Patent number: 7968425Abstract: Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first dielectric layer adjoining exposed substrate surfaces within the trench using a high-density plasma process, forming a layer of spin-on dielectric material on the first dielectric layer so as to fill a remaining portion of the trench, and densifying the layer of spin-on dielectric material.Type: GrantFiled: July 14, 2006Date of Patent: June 28, 2011Assignee: Micron Technology, Inc.Inventors: Zailong Bian, Xiaolong Fang
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Publication number: 20100062580Abstract: Trench isolation structures and methods to form same for use in the manufacture of semiconductor devices are described. The trench isolation structures are formed using several processing schemes that utilize disclosed dry etching processes to form a significant depth ? between an array trench depth and a periphery trench depth. One etching method creates a trench delta depth utilizing a single dry etch step, while two other etching methods create a trench ? depth by utilizing three dry etch steps.Type: ApplicationFiled: March 3, 2009Publication date: March 11, 2010Applicant: Micron Technology, Inc.Inventors: Xiaolong Fang, Ramakanth Alapati, Tuman E. Allen
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Publication number: 20090278227Abstract: Among structures, methods, devices, and systems for isolation trenches, a semiconductor device is provided that includes a substrate and an isolation trench structure. One such isolation trench structure includes a first isolation trench portion associated with a surface of the substrate and having a first pair of opposing sidewalls that are each substantially perpendicular to the surface of the substrate. A second isolation trench portion includes a second pair of sidewalls within the substrate that are each angled obliquely with respect to the surface of the substrate, where the second isolation trench portion has a separation between the second pair of sidewalls that decreases as a distance from the first isolation trench portion increases. A third isolation trench portion includes a third pair of sidewalls within the substrate that are each substantially perpendicular to the surface of the substrate.Type: ApplicationFiled: May 8, 2008Publication date: November 12, 2009Applicant: Micron Technology, Inc.Inventors: Michael A. Smith, Xiaolong Fang