Abstract: A display panel and a liquid crystal display device are provided. The display panel includes a first substrate and a second substrate, a sealant, a display layer, a circuit layer, and an organic film layer. The organic film layer includes vias and planarization portions arranged adjoining the vias. A first conductive layer includes conductive pads, and each conductive pad covers a signal line in at least one via and the planarization portion adjoining the vias. A second conductive layer is disposed on one side of the second substrate. A conductive ball of the sealant is located on the planarization portions and contact the first conductive layer and the second conductive layer. The signal line is electrically connected to the second conductive layer through the conductive pad and the conductive ball.

Abstract: Disclosed are an array substrate and a display panel. In the same frame, one of the first data line and the second data line accesses a positive polarity signal, and the other of the first data line and the second data line accesses a negative polarity signal; the first pixel electrode is electrically connected to the first data line, and the second pixel electrode is electrically connected to the second data line; the first shared electrode accesses a signal of the same polarity as the first data line, and the second shared electrode accesses a signal of the same polarity as the second data line.

Abstract: The disclosure provides an array substrate and a display panel. The array substrate includes a plurality of data lines, a plurality of scan lines, a plurality of clock signal lines, and a plurality of pixel units formed by the data lines and the scan lines horizontally and vertically crossing each other. The data lines are disposed between two adjacent columns of the pixel units. The scan lines are disposed between two adjacent rows of the pixel units. The clock signal lines in an opening area of the pixel units are disposed in a plurality of orthographic projection areas of a plurality of trunk electrodes, are parallel to the data lines, and are disposed in a different layer from a pixel electrode.

Abstract: A GOA circuit and a display panel are provided. The GOA circuit includes a plurality of GOA units connected in series. Each GOA unit includes a pull-up control module, a pull-up module, a download module, a pull-down maintaining module, a pull-down module, and a bootstrap capacitor. An AC signal applied to the pull-up module has high and low voltage levels. The high voltage level of the AC signal could reduce the rising time and the falling time of the conventional clock signal such that the output of the scan signal could be better. The low voltage level of the AC signal could pull down the signal in the blank time to perform a stress recovery such that the threshold voltage shift of the transistor caused by the high voltage level stress is reduced. This could raise the stability and the lifetime of the circuit.

Abstract: A GOA circuit and a display panel are disclosed. The GOA unit includes a plurality of stages of cascaded GOA units. Each GOA unit includes a pull-up control module, a pull-up module, a down transmission module, a pull-down remaining module, a pull-down module and a bootstrap capacitor. The pull-up module is deployed with two thin-film transistors, to which different oscillating signals are inputted, having individual output ports. The two transistors can operate alternatively for reducing the time a single thin-film transistor operates, lowering the shift of a threshold voltage and extending a lifespan of the device.

Abstract: A GOA circuit and a display panel are provided. The GOA circuit includes a plurality of GOA units connected in series. Each GOA unit includes a pull-up control module, a pull-up module, a download module, a pull-down maintaining module, a pull-down module, and a bootstrap capacitor. An AC signal applied to the pull-up module has high and low voltage levels. The high voltage level of the AC signal could reduce the rising time and the falling time of the conventional clock signal such that the output of the scan signal could be better. The low voltage level of the AC signal could pull down the signal in the blank time to perform a stress recovery such that the threshold voltage shift of the transistor caused by the high voltage level stress is reduced. This could raise the stability and the lifetime of the circuit.

Abstract: The disclosure provides an array substrate and a display panel. The array substrate includes a plurality of data lines, a plurality of scan lines, a plurality of clock signal lines, and a plurality of pixel units formed by the data lines and the scan lines horizontally and vertically crossing each other. The data lines are disposed between two adjacent columns of the pixel units. The scan lines are disposed between two adjacent rows of the pixel units. The clock signal lines in an opening area of the pixel units are disposed in a plurality of orthographic projection areas of a plurality of trunk electrodes, are parallel to the data lines, and are disposed in a different layer from a pixel electrode.

Abstract: A GOA circuit and a display panel are disclosed. The GOA unit includes a plurality of stages of cascaded GOA units. Each GOA unit includes a pull-up control module, a pull-up module, a down transmission module, a pull-down remaining module, a pull-down module and a bootstrap capacitor. The pull-up module is deployed with two thin-film transistors, to which different oscillating signals are inputted, having individual output ports. The two transistors can operate alternatively for reducing the time a single thin-film transistor operates, lowering the shift of a threshold voltage and extending a lifespan of the device.

Abstract: The present invention provides a driving circuit and a display panel including at least two gate driving units, and at least two of the gate driving units are connected in a cascade arrangement. an Nth stage driving unit in the at least two of the gate driving units includes a pull-up control module, a pull-up module, a pull-down module, a pull-down maintaining module, and a bootstrap capacitor, wherein N is an integer greater than 0.

Abstract: The present application discloses an array substrate and a liquid crystal display panel. The array substrate includes an underlay substrate, a first electrode layer, a protection layer, and a second electrode layer that are disposed sequentially. The second electrode layer includes a pixel electrode, and the pixel electrode includes a pixel electrode main body and a conductive portion connected to each other. A rough surface is disposed on the conductive portion for draining redundant alignment liquid on the conductive portion such that a thickness of an alignment layer formed by curing the alignment liquid is even.

Abstract: The present application discloses an array substrate and a liquid crystal display panel. The array substrate includes an underlay substrate, a first electrode layer, a protection layer, and a second electrode layer that are disposed sequentially. The second electrode layer includes a pixel electrode, and the pixel electrode includes a pixel electrode main body and a conductive portion connected to each other. A rough surface is disposed on the conductive portion for draining redundant alignment liquid on the conductive portion such that a thickness of an alignment layer formed by curing the alignment liquid is even.

Abstract: The present invention provides a driving circuit and a display panel including at least two gate driving units, and at least two of the gate driving units are connected in a cascade arrangement. an Nth stage driving unit in the at least two of the gate driving units includes a pull-up control module, a pull-up module, a pull-down module, a pull-down maintaining module, and a bootstrap capacitor, wherein N is an integer greater than 0.

Abstract: An array substrate and a display panel are provided. The array substrate includes a base substrate and a plurality of pixel units distributed in an array on the base substrate. The pixel unit includes a common electrode and a pixel electrode positioned above the common electrode. Meanwhile, the pixel electrode includes a main electrode and a branch electrode electrically connected to the main electrode, and an orthographic projection of the common electrode on the base substrate coincides with at least a part of an orthographic projection of the main electrode on the base substrate.

Abstract: A gate-on-array (GOA) driving circuit is provided, and the GOA driving circuit includes a plurality of cascading GOA driving units. Each of the GOA driving units further includes a first GOA driving sub-unit including a first signal source and a second GOA driving sub-unit including a second signal source. The first GOA driving sub-unit operates when the first signal source transmits a first signal with a high voltage, and the second GOA driving sub-unit transmitting a second signal operates when the first signal source transmits the first signal with a low voltage.

Abstract: The present invention discloses a gate-on-array (GOA) circuit with bidirectional outputs and a seamlessly-joined screen. The GOA circuit includes a first circuit, a pull-up module, a first output end, a second output end, a capacitor and a 41st transistor, wherein the capacitor and the second output end are connected in parallel and the 41st transistor and the first circuit are connected in parallel, and wherein the pull-up module is connected to the first circuit, the first circuit is connected to one of the first output end and the second output end, and the first output end is connected to a pull-down module.

Abstract: The present invention provides an array substrate and a liquid crystal display panel. The array substrate includes a substrate, a scan line, a data line, a thin film transistor, and a pixel electrode. The pixel electrode includes a trunk region and a branch region. In the pixel electrode, the data line is disposed along the trunk region. The present invention, by disposing the opaque data line in a region in which a trunk region of the opaque pixel electrode is located, reduces opaque regions of the array substrate and enhance the aperture ratio of the array substrate, which facilitates display quality of the liquid crystal display panel.

Abstract: An array substrate and a display panel are provided. The array substrate includes a base substrate and a plurality of pixel units distributed in an array on the base substrate. The pixel unit includes a common electrode and a pixel electrode positioned above the common electrode. Meanwhile, the pixel electrode includes a main electrode and a branch electrode electrically connected to the main electrode, and an orthographic projection of the common electrode on the base substrate coincides with at least a part of an orthographic projection of the main electrode on the base substrate.

Abstract: The present invention provides an array substrate and a liquid crystal display panel. The array substrate includes a substrate, a scan line, a data line, a thin film transistor, and a pixel electrode. The pixel electrode includes a trunk region and a branch region. In the pixel electrode, the data line is disposed along the trunk region. The present invention, by disposing the opaque data line in a region in which a trunk region of the opaque pixel electrode is located, reduces opaque regions of the array substrate and enhance the aperture ratio of the array substrate, which facilitates display quality of the liquid crystal display panel.

Abstract: A gate-on-array (GOA) driving circuit is provided, and the GOA driving circuit includes a plurality of cascading GOA driving units. Each of the GOA driving units further includes a first GOA driving sub-unit including a first signal source and a second GOA driving sub-unit including a second signal source. The first GOA driving sub-unit operates when the first signal source transmits a first signal with a high voltage, and the second GOA driving sub-unit transmitting a second signal operates when the first signal source transmits the first signal with a low voltage.

Abstract: A thin film transistor array substrate includes: a substrate on which a thin film transistor and a storage capacitor are formed. The storage capacitor includes a first electrode plate formed on the substrate, a gate isolation layer or an etching stopper layer formed on the first electrode plate, and a second electrode plate formed on the gate isolation layer or the etching stopper layer. The etching stopper layer may be formed on the gate isolation layer, of which one is partially etched and removed such that there is only one of the gate isolation layer and the etching stopper layer existing between the two electrode plates of the storage capacitor so as to reduce the overall thickness of the isolation layer of the storage capacitor. Thus, the capacitor occupies a smaller area and a higher aperture ratio may be achieved.