Patents by Inventor Xiaoyang Li

Xiaoyang Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11352354
    Abstract: A type of substituted penta-fused hexa-heterocyclic compounds having selective inhibition for PIKfyve kinase, a pharmaceutically acceptable salt and pharmaceutically acceptable solvate thereof, a method for the preparation thereof, a pharmaceutical composition comprising the same, and use of these compounds in the manufacture of a medicament for preventing or treating a disease associated with PIKfyve in vivo, in particular in the manufacture of a medicament for preventing or treating tumor growth and metastasis.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: June 7, 2022
    Assignee: Xiamen University
    Inventors: Xianming Deng, Wei Huang, Xihuan Sun, Ting Zhang, Zhixiang He, Yan Liu, Xinrui Wu, Baoding Zhang, Xiaoyang Li, Jingfang Zhang, Yun Chen, Li Li, Qingyan Xu, Zhiyu Hu
  • Patent number: 11345844
    Abstract: An oil well cement slurry high-temperature suspension stabilizer prepared from oil-based shale drilling cuttings is provided. The high-temperature suspension stabilizer is reasonable in principle, inexpensive and easily available in raw materials, high in product uniformity and good in chemical stability. Meanwhile, waste is changed into wealth. Therefore, the high-temperature suspension stabilizer is environment-friendly and has a broad industrial application prospect.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: May 31, 2022
    Assignees: SOUTHWEST PETROLEUM UNIVERSITY, SOUTHWEST PETROLEUM UNIVERSITY ENVIORMENTAL PROTECTION TECHNOLOGY (CHENGDU) CO., LTD
    Inventors: Xiaowei Cheng, Gaoyin Zhang, Shunxiang Luo, Zuwei Chen, Sheng Huang, Kaiqiang Liu, Chunmei Zhang, Kaiyuan Mei, Jian Liu, Zaoyuan Li, Xiaoyang Guo
  • Publication number: 20220155432
    Abstract: The present disclosures discloses a method of target feature extraction based on millimeter-wave radar echo, which mainly solves the problems that techniques in the prior art cannot fully utilize raw radar echo information to obtain more separable features and cannot accurately distinguish targets with similar physical shapes and motion states. The method is implemented as follows: acquiring measured data of targets, generating an original RD map, and removing ground clutter of the map; sequentially performing target detection, clustering and centroid condensation on the RD map after the ground clutter removal; acquiring a continuous multi-frame RD maps and carrying out the target tracking; according to the tracking trajectory, selecting candidate areas and extracting features based on a single piece of RD map and features based on two successive RD maps, respectively.
    Type: Application
    Filed: July 21, 2021
    Publication date: May 19, 2022
    Applicant: XIDIAN UNIVERSITY
    Inventors: LAN DU, ZENGYU YU, XIAOYANG CHEN, ZENGHUI LI, CHUNXIN WANG
  • Patent number: 11319322
    Abstract: The present invention relates to a compound having the following formula, or a stereoisomer thereof, a prodrug thereof, a pharmaceutically acceptable salt thereof or a pharmaceutically acceptable solvate thereof, preparation method thereof, pharmaceutical composition comprising the same and use of the compound in the manufacture of a medicament for preventing or treating tumor, wherein the substituents are as defined in the specification.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 3, 2022
    Assignee: Xiamen University
    Inventors: Xianming Deng, Ting Zhang, Qiaofeng Kang, Yanru Yang, Xihuan Sun, Zaiyou Yang, Xiaoyang Li, Jingfang Zhang, Jiaji Zhong, Zhou Deng, Chao Dong, Shuang Liu, Li Li, Qingyan Xu, Zhiyu Hu
  • Patent number: 11301297
    Abstract: A processing system includes at least one core, at least one accelerator function unit (AFU), a microcontroller, and a memory access unit. The AFU and the core share a plurality of virtual addresses to access a memory. The microcontroller is coupled between the core and the AFU. The core develops and stores a task in one of the virtual addresses. The microcontroller analyzes the task and dispatches the task to the AFU. The AFU accesses the virtual address indicating where the task is stored through the memory access unit to executes the task.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: April 12, 2022
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Xiaoyang Li, Chen Chen, Zongpu Qi, Tao Li, Xuehua Han, Wei Zhao, Dongxue Gao
  • Patent number: 11256633
    Abstract: A processing system includes at least one core, a plurality of accelerator function unit (AFU) and a memory access unit. The memory access unit includes at least one pipeline resource and an arbitrator. The core develops a plurality of tasks. Each of the AFU is used to execute at least one of the tasks which corresponds to several memory access requests. The arbitrator selects one of the AFUs using a round-robin method at each clock period to transmit a corresponding memory access request of the selected AFU to the pipeline resource, so that the selected AFU executes the memory access request through the pipeline resource to read or write data related to the task.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: February 22, 2022
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Xiaoyang Li, Chen Chen, Zongpu Qi, Tao Li, Xuehua Han, Wei Zhao, Dongxue Gao
  • Patent number: 11214806
    Abstract: Disclosed is a marker for observing an effect of a compound or a drug on cells in real time. The marker is: 1) an amino acid sequence shown in SEQ No. 1 and/or SEQ No. 2; or 2) an amino acid sequence having a function for observing an effect of a compound or a drug on cells in real time and having at least more than 80%, preferably more than 85%, more preferably 90%, further preferably 95%, and most preferably 99% homology with the amino acid sequence shown in SEQ No. 1 and/or SEQ No. 2. Also disclosed is a method and a kit for observing an effect of a compound or a drug on cells in real time and use thereof.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: January 4, 2022
    Assignee: Foshan University
    Inventors: Shen Quan Pan, Qinghua Yang, Xiaoyang Li, Haitao Tu
  • Publication number: 20210300949
    Abstract: A multifunctional immunity-targeted micromolecule anti-cancer medicine Citrate Bestazomib and preparation method and application thereof. The structure of the multifunctional immunity-targeted micromolecule anti-cancer medicine Bestazomib Citrate is shown as follows: The multifunctional immunity-targeted micromolecule anti-cancer medicine Citrate Bestazomib has an activity-inhibiting effect on APN/CD13, also has an activity-inhibiting effect on tumor proteasome, and can be applied to the development of medicines for treating malignant tumors.
    Type: Application
    Filed: August 5, 2019
    Publication date: September 30, 2021
    Inventors: Wenfang XU, Jian ZHANG, Yuqi JIANG, Xiaobo XU, Xiaoyang LI, Leqiao TAN, Yongxue HUANG, Xuejian WANG, Zhen ZHANG
  • Patent number: 11003445
    Abstract: A microprocessor for neural network computing having a mapping table, a microcode memory, and a microcode decoding finite-state machine (FSM) is disclosed. According to the mapping table, a macroinstruction is mapped to an address on the microcode memory. The microcode decoding FSM decodes contents which are retrieved from the microcode memory according to the address, to get microinstructions involving at least one microinstruction loop that is repeated to operate a datapath to complete the macroinstruction.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: May 11, 2021
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Jing Chen, Xiaoyang Li, Juanli Song, Zhenhua Huang, Weilin Wang, Jiin Lai
  • Publication number: 20210056005
    Abstract: A performance analysis system and method for analyzing processing performance of a processing device. A picker module is placed in the processing device to capture a plurality of pieces of time information of a unit circuit of each of a plurality of tasks in the processing device during total execution time of processing the plurality of tasks. A calculation circuit performs an interval analysis operation on the time information. The interval analysis operation includes: calculating an overlap period between a current task and a previous task; and counting time occupied by the unit circuit during the total execution time of processing the tasks by the processing device according to a relation between the current time interval of the current task corresponding to the unit circuit and the overlap period.
    Type: Application
    Filed: June 9, 2020
    Publication date: February 25, 2021
    Applicant: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventors: Lin Li, Xiaoyang Li, Zhiqiang Hui, Zheng Wang, Zongpu Qi
  • Patent number: 10929187
    Abstract: A processing system includes a core, at least one accelerator function unit (AFU) and an accelerator interface. The core is utilized to develop at least one task. The AFU is utilized to execute the task. The accelerator interface is arranged between the core and the AFU to receive an accelerator interface instruction transmitted by the processing core and instruct the AFU to execute the task according to the accelerator interface instruction.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: February 23, 2021
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Xiaoyang Li, Chen Chen, Zongpu Qi, Tao Li, Xuehua Han, Wei Zhao, Dongxue Gao
  • Patent number: 10891082
    Abstract: The invention introduces a method for accelerating compression, performed by configuration logic of a compression accelerator, containing: obtaining an input parameter from a processor core; obtaining a configuration setting from a compression parameter table according to the input parameter; configuring hardware coupled between a first buffer and a second buffer to form a data transmission path according to the input parameter, wherein the first buffer stores raw data; and transmitting the configuration setting to devices on the data transmission path for processing the raw data to generate compressed data and storing the compressed data in the second buffer.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: January 12, 2021
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Fangfang Wu, Shican Luo, Xiaoyang Li, Jin Yu, Lei Meng
  • Patent number: 10879926
    Abstract: An accelerated compression method and apparatus are provided. The accelerated compression apparatus includes a look-ahead buffer, a string matching processing pipeline and a control circuit. The string to be compressed extracted from the data register is stored to the look-ahead buffer. A string to be compressed includes Q characters, and a repeat flag is stored in the look-ahead buffer for each character in the string to be compressed. P instances are issued in parallel in each issue cycle. When all the characters included in P substrings corresponding to the P instances are identical to each other, the control circuit sets the repeat flags of the start characters corresponding to the last (P?1) instances among the P instances to a set state.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: December 29, 2020
    Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventors: Lin Li, Zheng Wang, Xiaoyang Li, Zongpu Qi
  • Publication number: 20200334176
    Abstract: A processing system includes at least one core, a plurality of accelerator function units (AFU) and a memory access unit. The memory access unit includes several schedulers and a pipeline resource. The core develops several tasks. Each AFU is used to execute one of the tasks correspondingly in association with memory several access requests. Each scheduler corresponds to each AFU for sorting the memory access requests based on the sequence in which the memory access requests were received from the corresponding AFU. The pipeline resource receives and executes memory access requests transmitted by the scheduler, and it transmits execution results of the memory access request to the corresponding AFU through each scheduler after executing the memory access request.
    Type: Application
    Filed: September 3, 2019
    Publication date: October 22, 2020
    Inventors: XIAOYANG LI, CHEN CHEN, ZONGPU QI, TAO LI, XUEHUA HAN, WEI ZHAO, DONGXUE GAO
  • Publication number: 20200334086
    Abstract: A processing system includes a core, at least one accelerator function unit (AFU) and an accelerator interface. The core is utilized to develop at least one task. The AFU is utilized to execute the task. The accelerator interface is arranged between the core and the AFU to receive an accelerator interface instruction transmitted by the processing core and instruct the AFU to execute the task according to the accelerator interface instruction.
    Type: Application
    Filed: September 3, 2019
    Publication date: October 22, 2020
    Inventors: XIAOYANG LI, CHEN CHEN, ZONGPU QI, TAO LI, XUEHUA HAN, WEI ZHAO, DONGXUE GAO
  • Publication number: 20200334087
    Abstract: A processing system includes at least one core, at least one accelerator function unit (AFU), a microcontroller, and a memory access unit. The AFU and the core share a plurality of virtual addresses to access a memory. The microcontroller is coupled between the core and the AFU. The core develops and stores a task in one of the virtual addresses. The microcontroller analyzes the task and dispatches the task to the AFU. The AFU accesses the virtual address indicating where the task is stored through the memory access unit to executes the task.
    Type: Application
    Filed: September 3, 2019
    Publication date: October 22, 2020
    Inventors: XIAOYANG LI, CHEN CHEN, ZONGPU QI, TAO LI, XUEHUA HAN, WEI ZHAO, DONGXUE GAO
  • Publication number: 20200334178
    Abstract: A processing system includes at least one core, a plurality of accelerator function unit (AFU) and a memory access unit. The memory access unit includes at least one pipeline resource and an arbitrator. The core develops a plurality of tasks. Each of the AFU is used to execute at least one of the tasks which corresponds to several memory access requests. The arbitrator selects one of the AFUs using a round-robin method at each clock period to transmit a corresponding memory access request of the selected AFU to the pipeline resource, so that the selected AFU executes the memory access request through the pipeline resource to read or write data related to the task.
    Type: Application
    Filed: September 3, 2019
    Publication date: October 22, 2020
    Inventors: XIAOYANG LI, CHEN CHEN, ZONGPU QI, TAO LI, XUEHUA HAN, WEI ZHAO, DONGXUE GAO
  • Patent number: 10776108
    Abstract: A microprocessor provides at least two storage areas and uses a datapath for Booth multiplication. According to a first and second field of a microinstruction, the datapath gets multiplicand number supply data from the first storage area and multiplier number supply data from the second storage area. The datapath operates according to a word length indicated in a third field of the microinstruction. The datapath gets multi-bit acquisitions for Booth multiplication from the multiplier number supply data. The datapath divides the multiplicand number supply data into multiplicand numbers according to the word length, and performs Booth multiplication on the multiplicand numbers based on the multi-bit acquisitions to get partial products. According to the word length, the datapath selects a part of the partial products to be shifted and added for generation of a plurality of products.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: September 15, 2020
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Jing Chen, Xiaoyang Li, Juanli Song, Zhenhua Huang, Weilin Wang, Jiin Lai
  • Patent number: 10776109
    Abstract: A microprocessor with dynamically adjustable bit width is provided, which has a bit width register, a datapath, a statistical register, and a bit width adjuster. The bit width register stores at least one bit width. The datapath operates according to the bit width stored in the bit width register to acquire input operands from received data and process input operands. The statistical register collects calculation results of the datapath. The bit width adjuster adjusts the bit width stored in the bit width register based on the calculation results collected in the statistical register.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: September 15, 2020
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Jing Chen, Xiaoyang Li, Juanli Song, Zhenhua Huang, Weilin Wang, Jiin Lai
  • Patent number: 10754648
    Abstract: A microprocessor having the capability of executing a micro-instruction for series calculation is provided. The microprocessor includes an instruction decoder and an execution circuit for series calculation. The micro-instruction whose source operands correspond to an undetermined number x and a plurality of coefficients a0 to an (for x0 to xn) is decoded by the instruction decoder. Based on x and a0 to an, the execution circuit for series calculation includes at least one multiplier for calculating exponentiation values of x (e.g. xp), and includes at least one MAU (multiply-and-accumulate unit) for combining x, the exponentiation values of x, and the coefficients a0 to an for the series calculation.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: August 25, 2020
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Jing Chen, Xiaoyang Li, Weilin Wang, Jiin Lai