Patents by Inventor Xin Gu

Xin Gu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200089107
    Abstract: An embodiment of this disclosure provides a nano-imprinting method, including: applying an imprinting adhesive on a to-be-processed layer of a substrate located in an imprinting chamber; charging the imprinting chamber with a preset gas at a temperature higher than a boiling point of the preset gas, and pressing a nano-imprinting template on the imprinting adhesive; reducing an ambient temperature of the imprinting chamber to a temperature lower than the boiling point of the preset gas and maintaining the temperature for a preset time, such that the preset gas becomes a liquid; irradiating ultraviolet light from a side of the nano-imprinting template away from the imprinting adhesive to cure the imprinting adhesive; raising the ambient temperature of the imprinting chamber to be higher than the boiling point of the preset gas, such that the liquefied preset gas turns back into a gas; and demolding the nano-imprinting template from the imprinting adhesive.
    Type: Application
    Filed: May 13, 2019
    Publication date: March 19, 2020
    Inventors: Yanhui Lu, Xin Gu, Kang Guo, Zhen Liu, Xiao Zhang, Wei Tan
  • Publication number: 20200081262
    Abstract: There is provided a holographic display device, which includes a display panel including plural sub-pixels, wherein each sub-pixel includes plural subdivided pixels, and each subdivided pixel has an adjustable light transmittance; a backlight, configured to provide reference light to the display panel; a phase adjustment layer, including plural transparent phase adjustment components, wherein each phase adjustment component is configured to adjust a phase of a light ray transmitted through the phase adjustment component, and the phase adjustment components corresponding to a single sub-pixel have phase adjustment amounts different from each other; and a controller, configured to obtain a target phase of a light ray to be transmitted through each sub-pixel, and determine a target subdivided pixel, which corresponds to the target phase, in each sub-pixel, and further configured to obtain a target intensity of the light ray, and adjust a light transmittance of the target subdivided pixel.
    Type: Application
    Filed: July 25, 2017
    Publication date: March 12, 2020
    Inventors: Jifeng TAN, Xue DONG, Wei WANG, Xiaochuan CHEN, Yafeng YANG, Xin GU, Feng GUAN, Meili WANG
  • Patent number: 10586000
    Abstract: The present disclosure relates to modeling the transient current of a partially simulated hierarchical gate-level electronic design. Embodiments may include providing a partially simulated hierarchical gate-level electronic design, wherein the design includes a design hierarchy having one or more leaf blocks associated therewith. Embodiments may also include identifying activity of sequential elements of the leaf blocks using simulation vectors, wherein the activity is used to estimate an amount of current associated with the sequential elements. Embodiments may further include computing an adaptive activity of a parent block of the leaf blocks, wherein the adaptive activity of the parent block corresponds to a weighted average of known activity of leaf blocks. Embodiments may also include generating an adaptive activity of a top block of the leaf blocks based upon the adaptive activity of the parent block and performing a mixed-mode simulation based upon the adaptive activity of the top block.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: March 10, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Anshu Mani, Bhuvnesh Kumar, Xin Gu
  • Patent number: 10579015
    Abstract: A reflective holographic display apparatus and a display method thereof are provided. The reflective holographic display apparatus includes a front light source module, a display panel and a phase plate. The front light source module is configured to provide reference lights; the display panel is configured to adjust amplitude information of the reference lights, wherein the display panel includes a reflective layer and the front light source module is located at a light exit side of the display panel; and the phase plate is configured to adjust phase information of the reference lights and located at a light exit side of the reflective layer.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: March 3, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jifeng Tan, Xue Dong, Wei Wang, Xin Gu, Feng Guan, Meili Wang
  • Patent number: 10566505
    Abstract: The present disclosure relates to a light-emitting diode (LED), including: a grating layer; and a light reflecting layer, wherein a light-emitting component is disposed between the grating layer and the light reflecting layer; and wherein the grating layer is configured to let linearly polarized light perpendicular to a grating direction of the grating layer in light emitted from the light-emitting component transmit through the grating layer, and reflect linearly polarized light parallel to the grating direction of the grating layer in the light emitted from the light-emitting component.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: February 18, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Kang Guo, Xin Gu, Wei Xu, Xiao Zhang, Zhen Liu
  • Patent number: 10552564
    Abstract: In general, the present embodiments are directed to designing an electronic system such as an IC, and more particularly to techniques for analyzing a design for potential ESD instance failures. Embodiments allow for efficiently determining a potential ESD violation or non-violation status for a large number of instances, such as all the instances in a full chip design, by performing effective resistance analyses between all the instances and all the bumps and ESD protection devices in the design. These and other embodiments further allow for more detailed effective resistance analyses to be performed for potential failing instances.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: February 4, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Nityanand Rai, Zhiyu Zeng, Xin Gu
  • Publication number: 20200033721
    Abstract: A nano-imprint template and a manufacturing method thereof are provided. The manufacturing method includes: forming a soft template on a side of at least one master provided with a preset pattern, wherein the soft template is provided with a groove corresponding to the preset pattern; forming a protective layer on a side of the soft template provided with the groove; moving at least one soft template formed with the protective layer into a stitching area of a base substrate; fixing at least one soft template on the base substrate, wherein the side of the soft template away from the protective layer contacts with the base substrate; and removing the protective layer.
    Type: Application
    Filed: May 22, 2019
    Publication date: January 30, 2020
    Inventors: Kang GUO, Xin GU
  • Patent number: 10544130
    Abstract: The present invention relates to metallo-?-lactamase inhibitor compounds of Formula I: and pharmaceutically acceptable salts thereof, wherein Z, RA, X1, X2 and R1 are as defined herein. The present invention also relates to compositions which comprise a metallo-?-lactamase inhibitor compound of the invention or a pharmaceutically acceptable salt thereof, and a pharmaceutically acceptable carrier, optionally in combination with a beta lactam antibiotic and/or a beta-lactamase inhibitor. The invention further relates to methods for treating a bacterial infection comprising administering to a patient a therapeutically effective amount of a compound of the invention, in combination with a therapeutically effective amount of one or more ?-lactam antibiotics and optionally in combination with one or more beta-lactamase inhibitor compounds. The compounds of the invention are useful in the methods described herein for overcoming antibiotic resistance.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: January 28, 2020
    Assignee: Merck Sharp & Dohme Corp.
    Inventors: Frank Bennett, Jinlong Jiang, Alexander Pasternak, Shuzhi Dong, Xin Gu, Jack D. Scott, Haiqun Tang, Zhiqiang Zhao, Yuhua Huang, Dexi Yang, Katherine Young, Li Xiao, Zhibo Zhang, Jianmin Fu
  • Patent number: 10540464
    Abstract: The present embodiments relate to critical path aware voltage drop analysis. A method can include identifying a number of cell instances with largest individual power consumption values. The method can include identifying, by performing static timing analysis, a first number of circuit timing paths of an integrated circuit design with largest timing violations. The method can include identifying, by performing the static timing analysis, a second number of circuit timing paths of the integrated circuit design. Each of the second number of circuit timing paths has a timing violation and is formed by one or more of the identified number of cell instances. The method can include generating logic state toggle vectors by propagating logic states through the first and second numbers of circuit timing paths. The method can include performing voltage drop analysis on the integrated circuit design using the generated logic state toggle vectors.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: January 21, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Suketu Desai, Anshu Mani, Apurva Soni, Shivani Sharma, Avnish Varma, Xin Gu
  • Patent number: 10515174
    Abstract: The present embodiments relate to generation of an interface model for performing a power analysis on a hierarchical integrated circuit design. According to some aspects, embodiments relate to a method of power analysis. The method can include partitioning an integrated circuit design into at least a first partition and a second partition sharing an interface with the first partition. The method can include generating a connectivity database of a signal net traversing from the first partition to the second partition across the first interface. The method can include determining a slew rate and a signal arrival time at the input pin of the destination cell, a capacitance load of the signal net, and one or more signal transitions and signal states on the signal net. The method can include calculating the power consumption of the circuit elements in the first partition using the connectivity database, and the determined information.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 24, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Avnish Varma, Rishabh, Xin Gu
  • Patent number: 10509246
    Abstract: A display panel and a driving method and manufacturing method thereof, and a display device. The display panel includes a base substrate, a dielectric layer provided on the base substrate, and a refractive index variable layer provided on a side of the dielectric layer away from the base substrate; the refractive index variable layer is in contact with the dielectric layer and has a contact surface with the dielectric layer, and the refractive index variable layer can change the refractive index so that the light entering from the light incident side is totally reflected or transmitted at the contact surface.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: December 17, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Xiao Zhang, Pengxia Liang, Kang Guo, Xin Gu
  • Patent number: 10503006
    Abstract: A reflective display includes a first substrate and a second substrate arranged oppositely, a first electrode provided on the first substrate, a transparent dielectric layer arranged on the side of the first substrate opposite to the second substrate, a second electrode provided on the second substrate, and immiscible electrostriction light-absorbing material and transparent liquid filled between the first substrate and the second substrate. The light incident into the reflective display can be totally reflected on the side of the transparent liquid next to the first substrate; the electrostriction light-absorbing material deforms under action of an electric field formed by the first electrode and the second electrode, which enables a spreading area of the side of the transparent liquid next to the first substrate change.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: December 10, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Kang Guo, Pengxia Liang, Xin Gu, Xiao Zhang
  • Patent number: 10476021
    Abstract: Embodiments of the present disclosure provide a light emitting diode, an array substrate, a light emitting device and a display device. The light emitting diode includes an anode, a hole transport layer, a light emitting layer, an electron transport layer, and a cathode sequentially disposed. The light emitting diode further includes a first auxiliary electrode and a first insulating layer which are disposed on a side of the anode away from the hole transport layer, wherein the first insulating layer is located between the first auxiliary electrode and the anode; and/or a second insulating layer and a second auxiliary electrode which are disposed on a side of the cathode away from the electron transport layer, wherein the second insulating layer is located between the second auxiliary electrode and the cathode.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 12, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Xu, Xin Gu
  • Patent number: 10459309
    Abstract: An electronic paper and a manufacturing method thereof are provided. The electronic paper includes a first substrate provided with a microstructure and multiple first electrodes thereon; a second substrate arranged opposite to the first substrate and provided with multiple second electrodes thereon, the microstructure is arranged on a side of the first substrate facing the second substrate; and pixel isolation walls arranged between the first and second substrates, for dividing the electronic paper into pixel units; each pixel unit includes: one first substrate; one second substrate; charged particles arranged between the first and second electrodes, the first and second electrodes control, depending on a voltage applied thereto, contact between the charged particles and the microstructure; when the charged particles are not in contact with the microstructure, light from outside is subject to total internal reflection after being radiated to the microstructure through the first substrate.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: October 29, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Xin Gu
  • Patent number: 10437043
    Abstract: A display panel and a manufacturing method thereof, and a display device are provided. The display panel includes a plurality of display units. Each display unit includes a first substrate and a second substrate opposite to each other. The first substrate includes a first base substrate and a first electrode, an electrostriction layer and a reflective trough which are disposed thereon. The second substrate includes a second base substrate and a second electrode and a reflective cavity body which are disposed thereon. A support is disposed between the first base substrate and the second base substrate, such that a distance between the first base substrate and the second base substrate is kept constant.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: October 8, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Pengxia Liang, Xin Gu, Kang Guo
  • Patent number: 10423754
    Abstract: In general, the present embodiments are directed to designing an electronic system such as an IC, and more particularly to a design technique that can determine an optimal number and placement of ESD cells in a design for an IC. In embodiments, the technique includes determining an effective resistance criteria between a set of candidate ESD cells to the bumps/pads of the IC and finding a minimum set of ESD cells that covers all the bumps/pads. In embodiments, the technique is employed at the early stage of the design of the IC.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: September 24, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Nityanand Rai, Xin Gu, Zhiyu Zeng
  • Publication number: 20190265521
    Abstract: A reflective display and a preparation method thereof are disclosed. The reflective display includes: a first substrate and a second substrate, a first electrode provided on the first substrate a transparent dielectric layer provided on a side of the first substrate, which side faces the second substrate, a second electrode provided on the second substrate, and liquid crystal located between the first substrate and the second substrate; a refractive index of the liquid crystal changes under action of an electric field formed by the first electrode and the second electrode so that the refractive index of the liquid crystal is the same as or substantially the same as a refractive index of the transparent dielectric layer, or less than the refractive index of the transparent dielectric layer.
    Type: Application
    Filed: September 6, 2017
    Publication date: August 29, 2019
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Pengxia LIANG, Xiao ZHANG, Xin GU
  • Publication number: 20190234942
    Abstract: The invention relates to methods of identifying compounds that modulate mTORC1 activity in a cell by modulating the activity of SAMTOR, as well as to the use of such identified compounds in the modulation of mTORC1 and the treatment of diseases and conditions characterized by aberrant mTORC1 activity.
    Type: Application
    Filed: October 18, 2018
    Publication date: August 1, 2019
    Inventors: David M. Sabatini, Xin Gu, Jose M. Orozco
  • Publication number: 20190212542
    Abstract: The disclosure provides a light-adjusting glass, including an outer light transmissive layer and an inner light transmissive layer, a microstructure layer bonded to or disposed on an inner surface of the outer light transmissive layer and provided with a reflective microstructure, a sealing member bonded to an end portion of the outer light transmissive layer and an end portion of the inner light transmissive layer, the sealing member, the microstructure layer and the inner light transmissive layer enclosing a space having a predetermined volume. A predetermined amount of a first substance is disposed within the space. The disclosure also provides a method for preparing a light-adjusting glass. The light-adjusting glass of the present disclosure does not require an electric field to control the light-adjusting.
    Type: Application
    Filed: May 15, 2018
    Publication date: July 11, 2019
    Inventors: Xiao ZHANG, Xin GU, Kang GUO
  • Publication number: 20190196401
    Abstract: A reflective holographic display apparatus and a display method thereof are disclosed. The reflective holographic display apparatus includes a front light source module, a display panel and a phase plate. The front light source module is configured to provide reference lights; the display panel is configured to adjust amplitude information of the reference lights, wherein the display panel includes a reflective layer and the front light source module is located at a light exit side of the display panel; and the phase plate is configured to adjust phase information of the reference lights and located at a light exit side of the reflective layer.
    Type: Application
    Filed: July 24, 2017
    Publication date: June 27, 2019
    Inventors: Jifeng Tan, Xue Dong, Wei Wang, Xin Gu, Feng Guan, Meili Wang