Patents by Inventor Xingshou Pang

Xingshou Pang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11784112
    Abstract: An integrated circuit package is formed by positioning an integrated circuit die on a die pad of a leadframe; connecting a bond wire between the die and a bond pad of the leadframe; encapsulating the bond wire, die, and bond pad with an encapsulant material to form a first mold cap of the integrated circuit package; after the encapsulating, bending one or more leads of the leadframe to form one or more bent leads; and encapsulating the first mold cap and a portion of a bend of the one or more bent leads with the encapsulant material to form a second mold cap.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 10, 2023
    Assignee: NXP USA, Inc.
    Inventors: Jian Song, Jun Li, Xingshou Pang, Mingchuan Han, Jinzhong Yao, Xuesong Xu
  • Publication number: 20220399257
    Abstract: An integrated circuit package is formed by positioning an integrated circuit die on a die pad of a leadframe; connecting a bond wire between the die and a bond pad of the leadframe; encapsulating the bond wire, die, and bond pad with an encapsulant material to form a first mold cap of the integrated circuit package; after the encapsulating, bending one or more leads of the leadframe to form one or more bent leads; and encapsulating the first mold cap and a portion of a bend of the one or more bent leads with the encapsulant material to form a second mold cap.
    Type: Application
    Filed: August 30, 2021
    Publication date: December 15, 2022
    Inventors: Jian Song, Jun Li, Xingshou Pang, Mingchuan Han, Jinzhong Yao, Xuesong Xu
  • Patent number: 11417541
    Abstract: A mold chase has first and second mold clamps having corresponding teeth and recesses configured such that, when the mold chase is closed onto a sub-assembly having an IC die mounted onto and wire-bonded to a lead frame, there are gaps between the recesses and the leads of the lead frame that allow molding compound to extend along opposing sides of proximal ends of the leads to increase the metal-to-metal distance between adjacent leads, thereby reducing the chances of, for example, tin migrating during HAST testing to form undesirable conduction paths between adjacent leads. In some embodiments, the mold clamp teeth have chamfered edges that are tapered at the mold chase cavity to form wedge-shaped gaps that allow the molding compound to extrude along the proximal ends of the leads of MaxQFP packages having two levels of ā€œJā€ leads and gullwing leads.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 16, 2022
    Assignee: NXP USA, INC.
    Inventors: Zhigang Bai, Jinzhong Yao, Xingshou Pang
  • Publication number: 20210066092
    Abstract: A mold chase has first and second mold clamps having corresponding teeth and recesses configured such that, when the mold chase is closed onto a sub-assembly having an IC die mounted onto and wire-bonded to a lead frame, there are gaps between the recesses and the leads of the lead frame that allow molding compound to extend along opposing sides of proximal ends of the leads to increase the metal-to-metal distance between adjacent leads, thereby reducing the chances of, for example, tin migrating during HAST testing to form undesirable conduction paths between adjacent leads. In some embodiments, the mold clamp teeth have chamfered edges that are tapered at the mold chase cavity to form wedge-shaped gaps that allow the molding compound to extrude along the proximal ends of the leads of MaxQFP packages having two levels of ā€œJā€ leads and gullwing leads.
    Type: Application
    Filed: October 30, 2019
    Publication date: March 4, 2021
    Inventors: Zhigang Bai, Jinzhong Yao, Xingshou Pang
  • Patent number: 10515880
    Abstract: A lead frame for a packaged integrated circuit (IC) device has a die receiving area and leads that extend outwardly from the die receiving area. The leads have an inner lead area proximate the die receiving area and an outer lead area distant from the die receiving area. Notches are formed in a surface of alternate ones of the leads, in the inner lead area proximate to the outer lead area. The notches facilitate bending of the alternate leads when the leads are subjected to a downward force by a mold tool, such that one set of leads lies in a first plane and another set lies in a second plane spaced from the first plane. The leads in the first plane can be formed into Gull Wing leads and the other set of leads into J-leads.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: December 24, 2019
    Assignee: NXP USA, INC
    Inventors: Jinzhong Yao, Zhigang Bai, Xingshou Pang, Meng Kong Lye, Xuesong Xu
  • Patent number: 10446476
    Abstract: A packaged integrated circuit (IC) device includes a first IC die with a first inductor, a first layer of adhesive on a first major surface of the first IC die, an isolation layer over the first layer of adhesive, a second layer of adhesive on the isolation layer, a second IC die on the second layer of adhesive, and a second inductor in the second IC die aligned to communicate with the first inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: October 15, 2019
    Assignee: NXP USA, Inc.
    Inventors: Leo M. Higgins, III, Fred T. Brauchler, Burton Jesse Carpenter, Jinmei Liu, Mariano Layson Ching, Jr., Jinzhong Yao, Xingshou Pang, Jianhong Wang, Yadong Wei
  • Publication number: 20190287883
    Abstract: A lead frame for a packaged integrated circuit (IC) device has a die receiving area and leads that extend outwardly from the die receiving area. The leads have an inner lead area proximate the die receiving area and an outer lead area distant from the die receiving area. Notches are formed in a surface of alternate ones of the leads, in the inner lead area proximate to the outer lead area. The notches facilitate bending of the alternate leads when the leads are subjected to a downward force by a mold tool, such that one set of leads lies in a first plane and another set lies in a second plane spaced from the first plane. The leads in the first plane can be formed into Gull Wing leads and the other set of leads into J-leads.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 19, 2019
    Inventors: Jinzhong Yao, Zhigang Bai, Xingshou Pang, Meng Kong Lye, Xuesong Xu
  • Publication number: 20190088576
    Abstract: A packaged integrated circuit (IC) device includes a first IC die with a first inductor, a first layer of adhesive on a first major surface of the first IC die, an isolation layer over the first layer of adhesive, a second layer of adhesive on the isolation layer, a second IC die on the second layer of adhesive, and a second inductor in the second IC die aligned to communicate with the first inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die.
    Type: Application
    Filed: March 19, 2018
    Publication date: March 21, 2019
    Inventors: LEO M. HIGGINS, III, Fred T. Brauchler, Burton Jesse Carpenter, Jinmei Liu, Mariano Layson Ching, JR., Jinzhong Yao, Xingshou Pang, Jianhong Wang, Yadong Wei
  • Patent number: 10217700
    Abstract: A lead frame for a packaged integrated circuit (IC) device has alternating first and second leads that protrude from a package body in respective first and second planes, where the second plane is parallel to and below the first plane. The first leads are formed into Gull Wing shaped leads and the second leads are formed into J-shaped leads. Inner lead portions of the first and second leads are maintained in the first plane with a tape. An inner lead portion of each of the second leads, proximate to and extending to the outer lead portion, is down-set, so that when the outer lead portion is pressed down by a mold tool to locate the outer lead portion of the second leads in the second plane, the inner lead portion of the second leads is maintained in the first plane and does not separate from the tape.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: February 26, 2019
    Assignee: NXP USA, INC.
    Inventors: Zhigang Bai, Jinzhong Yao, Xingshou Pang, Jun Li, Meng Kong Lye
  • Patent number: 10181434
    Abstract: A lead frame for a packaged integrated circuit (IC) device has alternating first and second leads that protrude from a package body in respective first and second planes, where the second plane is parallel to and below the first plane. The first leads are formed into Gull Wing shaped leads and the second leads are formed into J-shaped leads. Inner lead portions of the first and second leads are maintained in the first plane with a tape. An inner lead portion of each of the second leads includes a deformation area that facilitates maintaining the tape in contact with the inner lead area of the second leads, even when a mold tool presses down on an outer lead side of the second leads to place the outer lead ends of the second leads in the second plane.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: January 15, 2019
    Assignee: NXP USA, INC.
    Inventors: Xingshou Pang, Jinzhong Yao, Zhigang Bai, Meng Kong Lye
  • Patent number: 10037935
    Abstract: Embodiments of a lead frame for a packaged semiconductor device are provided, one embodiment including: a die pad; a first row of active lead fingers that are laterally separated from one another along their entire length; a package body perimeter that indicates placement of a package body of the packaged semiconductor device, wherein the package body perimeter is located laterally around the die pad; a first dummy lead finger positioned in parallel next to an initial active lead finger of the first row of active lead fingers, wherein the first dummy lead finger and the initial active lead finger are laterally separated from one another along their entire length, and wherein the first dummy lead finger is separated from the package body perimeter by a gap distance; and a first tie bar connected to an outside edge of the first dummy lead finger.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: July 31, 2018
    Assignee: NXP USA, Inc.
    Inventors: Xingshou Pang, Zhigang Bai, Jinzhong Yao, Yuan Zang
  • Patent number: 9443746
    Abstract: Tooling for molding a packaged semiconductor device includes a clamping plate, a cavity bar, and an attachment mechanism. The cavity bar has a mold half that has a mold cavity for molding the packaged semiconductor device. The mold half has teeth and a space between pairs of adjacent teeth. The teeth and the spaces support bending of leads of a lead frame of the packaged semiconductor device. The attachment mechanism affixes the cavity bar to the clamping plate and permits the cavity bar to slide relative to the clamping plate. This sliding of the cavity bar enables proper alignment with a mating cavity bar to reduce the likelihood of resin bleed.
    Type: Grant
    Filed: December 7, 2014
    Date of Patent: September 13, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Zhigang Bai, Xingshou Pang, Jinzhong Yao
  • Patent number: 9416002
    Abstract: A method for assembling a packaged semiconductor device includes mounting a pressure-sensing die onto a die paddle of a metal lead frame. A pressure-sensitive gel is dispensed into a recess of a lid, and the lead frame is mated with the lid such that the pressure-sensing die is immersed in the pressure-sensitive gel within the recess of the lid.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: August 16, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Nan Xu, Xingshou Pang, Xuesong Xu
  • Patent number: 9324637
    Abstract: A Quad Flat Non-leaded (QFN) semiconductor package has a semiconductor die mounted on a die flag of a lead frame. A molded housing with a base and sides covers the die. The package has electrically conductive mounting feet each of which includes an exposed base surface in the base of the housing, an opposite parallel surface covered by the housing, and an exposed end surface in the one of the sides of the housing. The exposed end surface is normal to, and located between, the exposed base surface and the opposite parallel surface. Bond wires selectively electrically connect electrodes of the die to respective ones of the mounting feet. An electrically conductive plating coats the exposed base portion and exposed end surface of the mounting feet.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: April 26, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Zhigang Bai, Xingshou Pang, Nan Xu, Jinzhong Yao
  • Publication number: 20160056097
    Abstract: A Quad Flat Non-leaded (QFN) semiconductor die package has a semiconductor die mounted on a die flag of a lead frame. A covers the semiconductor die. The housing has a base and sides. There are electrically conductive mounting feet, each of which has an exposed base portion in the base of the housing and an exposed side portion in the one of the sides of the housing. Bond wires electrically connect electrodes of the semiconductor die to respective ones of the mounting feet.
    Type: Application
    Filed: November 30, 2014
    Publication date: February 25, 2016
    Inventors: Zhigang Bai, Xingshou Pang, Nan Xu, Jinzhong Yao
  • Publication number: 20160049318
    Abstract: Tooling for molding a packaged semiconductor device includes a clamping plate, a cavity bar, and an attachment mechanism. The cavity bar has a mold half that has a mold cavity for molding the packaged semiconductor device. The mold half has teeth and a space between pairs of adjacent teeth. The teeth and the spaces support bending of leads of a lead frame of the packaged semiconductor device. The attachment mechanism affixes the cavity bar to the clamping plate and permits the cavity bar to slide relative to the clamping plate. This sliding of the cavity bar enables proper alignment with a mating cavity bar to reduce the likelihood of resin bleed.
    Type: Application
    Filed: December 7, 2014
    Publication date: February 18, 2016
    Inventors: Zhigang Bai, Xingshou Pang, Jinzhong Yao
  • Publication number: 20160023894
    Abstract: A method for assembling a packaged semiconductor device includes mounting a pressure-sensing die onto a die paddle of a metal lead frame. A pressure-sensitive gel is dispensed into a recess of a lid, and the lead frame is mated with the lid such that the pressure-sensing die is immersed in the pressure-sensitive gel within the recess of the lid.
    Type: Application
    Filed: December 4, 2014
    Publication date: January 28, 2016
    Inventors: Nan Xu, Xingshou Pang, Xuesong Xu
  • Patent number: 8692387
    Abstract: A semiconductor package and method of assembling a semiconductor package includes encapsulating a first pre-packaged semiconductor die stacked on top of and interconnected with a second semiconductor die. The first packaged semiconductor die is positioned and fixed relative to a lead frame with a temporary carrier such as tape. The second semiconductor die is attached and interconnected directly to the first packaged semiconductor die and lead frame. The interconnected first packaged die and second semiconductor die, and lead frame are encapsulated to form the semiconductor package. Different types of semiconductor packages such as quad flat no-lead (QFN) and ball grid array (BGA) may be formed, which provide increased input/output (I/O) count and functionality.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: April 8, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Shunan Qiu, Guoliang Gong, Xuesong Xu, Xingshou Pang, Beiyue Yan, Yinghui Li
  • Patent number: 8481369
    Abstract: A no-lead type semiconductor package is formed by attaching a die to a top surface of a flag of a lead frame and then taping a bottom surface of the flag and leads of the lead frame. Die bonding pads are connected to the leads with wires and then the assembly is put in a mold chase and encapsulated with a plastic material. The mold chase has protrusions between the flag and the leads of a lead frame, and between the leads themselves, which causes indentations to be formed between the leads and between the flag and the leads. The method is particularly useful for making quad flat no lead (QFN) devices and power-QFN type devices.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: July 9, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Junhua Luo, Xingshou Pang, Jinzhong Yao
  • Publication number: 20130049180
    Abstract: A lead frame for a quad flat no-lead (QFN) type semiconductor device package includes a die pad, a plurality of leads that surround the die pad. The outer edge of leads includes a channel that extends from a lower surface to an upper surface of the leads. A semiconductor die is attached to the die pad. An inner edge of each lead is electrically connected to a corresponding bonding pad on the semiconductor die. The assembly is covered with an encapsulation material except that the outer edge of each lead and the corresponding channel are exposed. The channel allows solder to flow up the outer edge of a lead when the QFN device is soldered to a substrate, which improves the ability to perform visual inspection of the solder-lead connection.
    Type: Application
    Filed: July 15, 2012
    Publication date: February 28, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Nan XU, Xingshou PANG, Bin TIAN, Shufeng ZHAO