Abstract: The disclosure provides a normally-off gallium oxide field-effect transistor structure and a preparation method therefor, and relates to the technical field of semiconductor device. The normally-off gallium oxide field-effect transistor structure comprises a substrate layer and an n-type doped gallium oxide channel layer from bottom to top. The n-type doped gallium oxide channel layer is provided with a source, a drain, and a gate. The gate is located between the source and the drain. A no-electron channel region is provided in the n-type doped gallium oxide channel layer located below the gate.

Abstract: Disclosed is a method for preparing a carbonized silk photocatalyst, comprising; soaking a natural silk and an activator in water, taking out the soaked silk, and drying the same; and roasting the dried silk under the protection of an inert atmosphere to prepare a carbonized silk photocatalyst. Also disclosed is a method for photocatalytic desulfurization of a fuel oil, comprising: mixing a fuel oil to be desulfurated, an extraction agent and a carbonized silk photocatalyst, with air being used as an oxidizing agent, to conduct a photocatalytic reaction under light irradiation, and separating an upper oil phase to obtain a desulfurated fuel oil. The catalyst has a simple preparation process, and can effectively reduce dibenzothiophene sulfides, which are difficult to remove, in the fuel oil under UV light radiation. Desulfurization can be achieved at room temperature, and reaction conditions are mild.

Abstract: The disclosure is applicable for the technical field of semiconductor devices manufacturing, and provides a gallium oxide SBD terminal structure. The gallium oxide SBD terminal structure comprises a cathode metal layer, an N+ high-concentration substrate layer, an N? low-concentration Ga2O3 epitaxial layer and an anode metal layer from bottom to top, wherein the N? low-concentration Ga2O3 epitaxial layer is within a range of certain thickness close to the anode metal layer; and a doping concentration below the anode metal layer is greater than a doping concentration on two sides of the anode metal layer. Namely, only a doping concentration of the part outside the corresponding area of the anode metal layer is changed, so that the breakdown voltage of the gallium oxide SBD terminal structure is improved under the condition of guaranteeing low on resistance.

Abstract: A receiver, a receiver assembly and a heat pump system. The receiver includes a first pipe, a second pipe and a third pipe leading to the cavity of the receiver, wherein the first pipe, the second pipe and the third pipe connect to a first load unit, a second load unit and a cold and heat source unit, respectively.

Abstract: A ultraviolet detector includes a substrate; a first epitaxial layer that is a heavily doped epitaxial layer and located on the substrate, a second epitaxial layer located on the first epitaxial layer, where the second epitaxial layer is a lightly doped epitaxial layer, or a double-layer or multi-layer structure composed of at least one lightly doped epitaxial layer and at least one heavily doped epitaxial layer; an ohmic contact layer located on the second epitaxial layer or formed in the second epitaxial layer, where the ohmic contact layer is a graphical heavily doped layer; and a first metal electrode layer located on the ohmic contact layer.

Abstract: The disclosure is related to the technical field of semiconductors, and provides a method for manufacturing a tilted mesa and a method for manufacturing a detector. The method for manufacturing a tilted mesa comprises: coating a photoresist layer on a mesa region of a chip; heating the chip on which the photoresist layer is coated from a first preset temperature to a second preset temperature; performing etching processing on the heated chip, so as to manufacture a mesa having a preset tilting angle; and removing the photoresist layer on the mesa region of the chip after the mesa is manufactured.

Abstract: A method for preparing an avalanche photodiode includes preparing a mesa on a wafer, growing a sacrificial layer on an upper surface of the wafer and a side surface of the mesa, removing the sacrificial layer in an ohmic contact electrode region of the wafer, preparing an ohmic contact electrode in the ohmic contact electrode region of the wafer, removing the sacrificial layer in a non-mesa region of the wafer, growing a passivation layer on the upper surface of the wafer and the side surface of the mesa, removing the passivation layer on the upper surface of the mesa of the wafer and the passivation layer in the non-mesa region of the wafer corresponding to the ohmic contact electrode region, and removing the sacrificial layer on the upper surface of the mesa of the wafer.

Abstract: The disclosure provides a silicon carbide detector and a preparation method therefor. The silicon carbide detector comprises: a wafer, the wafer sequentially comprises, from bottom to top, a substrate, a silicon carbide P+ layer, an N-type silicon carbide insertion layer, an N+ type silicon carbide multiplication layer, an N-type silicon carbide absorption layer and a silicon carbide N+ layer; the doping concentration of the N-type silicon carbide insertion layer gradually increases from bottom to top, and the doping concentration of the N-type silicon carbide absorption layer gradually decreases from bottom to top; a mesa is etched on the wafer, and the mesa is etched to an upper surface of the silicon carbide P+ layer; an N-type electrode is arranged on an upper surface of the mesa, and a P-type electrode is arranged on an upper surface of a non-mesa region.

Abstract: The present disclosure discloses a method for preparing an isolation area of a gallium oxide device, the method comprising: depositing a mask layer on a gallium oxide material; removing a preset portion region of the mask layer; preparing an isolation area in a position, corresponding to the preset portion region, on the gallium oxide material by using a high-temperature oxidation technique, with the isolation area being located between active areas of the gallium oxide device; and removing the remaining mask layer on the gallium oxide material. In the disclosure, the isolation area is prepared by using the high-temperature oxidation technique, which prevents damage to the gallium oxide device during the preparation of the isolation area, thereby achieving isolation between the active areas of the gallium oxide device.

Abstract: The present disclosure discloses an enhancement-mode field effect transistor. This enhancement-mode field effect transistor includes a substrate, a channel layer formed on an upper surface of the substrate, a source electrode and a drain electrode respectively formed on both sides of the channel layer, and a gate electrode formed on an upper surface of the channel layer, a region outside the corresponding region of the gate electrode in the channel layer is provided with a carrier-free region. Carriers are absent in the carrier-free region, and carriers are present in the remaining portion of the channel layer. The carrier-free region is not disposed below the gate electrode, but is disposed outside the corresponding region of the gate electrode in the channel layer, and the threshold voltage of the device can be regulated by regulating the width and number of the carrier-free region.

Abstract: The disclosure provides a normally-off gallium oxide field-effect transistor structure and a preparation method therefor, and relates to the technical field of semiconductor device. The normally-off gallium oxide field-effect transistor structure comprises a substrate layer and an n-type doped gallium oxide channel layer from bottom to top. The n-type doped gallium oxide channel layer is provided with a source, a drain, and a gate. The gate is located between the source and the drain. A no-electron channel region is provided in the n-type doped gallium oxide channel layer located below the gate.

Abstract: The disclosure is applicable for the technical field of semiconductor devices manufacturing, and provides a gallium oxide SBD terminal structure. The gallium oxide SBD terminal structure comprises a cathode metal layer, an N+ high-concentration substrate layer, an N? low-concentration Ga2O3 epitaxial layer and an anode metal layer from bottom to top, wherein the N? low-concentration Ga2O3 epitaxial layer is within a range of certain thickness close to the anode metal layer; and a doping concentration below the anode metal layer is greater than a doping concentration on two sides of the anode metal layer. Namely, only a doping concentration of the part outside the corresponding area of the anode metal layer is changed, so that the breakdown voltage of the gallium oxide SBD terminal structure is improved under the condition of guaranteeing low on resistance.

Abstract: A method for preparing an avalanche photodiode includes preparing a mesa on a wafer, growing a sacrificial layer on an upper surface of the wafer and a side surface of the mesa, removing the sacrificial layer in an ohmic contact electrode region of the wafer, preparing an ohmic contact electrode in the ohmic contact electrode region of the wafer, removing the sacrificial layer in a non-mesa region of the wafer, growing a passivation layer on the upper surface of the wafer and the side surface of the mesa, removing the passivation layer on the upper surface of the mesa of the wafer and the passivation layer in the non-mesa region of the wafer corresponding to the ohmic contact electrode region, and removing the sacrificial layer on the upper surface of the mesa of the wafer.

Abstract: The disclosure provides a silicon carbide detector and a preparation method therefor. The silicon carbide detector comprises: a wafer, the wafer sequentially comprises, from bottom to top, a substrate, a silicon carbide P+ layer, an N-type silicon carbide insertion layer, an N+ type silicon carbide multiplication layer, an N-type silicon carbide absorption layer and a silicon carbide N+ layer; the doping concentration of the N-type silicon carbide insertion layer gradually increases from bottom to top, and the doping concentration of the N-type silicon carbide absorption layer gradually decreases from bottom to top; a mesa is etched on the wafer, and the mesa is etched to an upper surface of the silicon carbide P+ layer; an N-type electrode is arranged on an upper surface of the mesa, and a P-type electrode is arranged on an upper surface of a non-mesa region.

Abstract: The disclosure is related to the technical field of semiconductors, and provides a method for manufacturing a tilted mesa and a method for manufacturing a detector. The method for manufacturing a tilted mesa comprises: coating a photoresist layer on a mesa region of a chip; heating the chip on which the photoresist layer is coated from a first preset temperature to a second preset temperature; performing etching processing on the heated chip, so as to manufacture a mesa having a preset tilting angle; and removing the photoresist layer on the mesa region of the chip after the mesa is manufactured.

Abstract: The present disclosure discloses a method for preparing an isolation area of a gallium oxide device, the method comprising: depositing a mask layer on a gallium oxide material; removing a preset portion region of the mask layer; preparing an isolation area in a position, corresponding to the preset portion region, on the gallium oxide material by using a high-temperature oxidation technique, with the isolation area being located between active areas of the gallium oxide device; and removing the remaining mask layer on the gallium oxide material. In the disclosure, the isolation area is prepared by using the high-temperature oxidation technique, which prevents damage to the gallium oxide device during the preparation of the isolation area, thereby achieving isolation between the active areas of the gallium oxide device.

Abstract: An enhanced HFET, comprising a HFET device body.

Abstract: The present disclosure relates to semiconductor devices, and in particular, to an enhancement-mode field effect transistor. This enhancement-mode field effect transistor includes a substrate, a channel layer formed on an upper surface of the substrate, a source electrode and a drain electrode respectively formed on both sides of the channel layer, and a gate electrode formed on an upper surface of the channel layer, a region outside the corresponding region of the gate electrode in the channel layer is provided with a carrier-free region. Carriers are absent in the carrier-free region, and carriers are present in the remaining portion of the channel layer.

Abstract: An enhanced HFET, comprising a HFET device body.

Abstract: A method for preparing a cap-layer-structured gallium oxide field effect transistor, includes: removing a gallium oxide channel layer and a gallium oxide cap layer from a passive area of a gallium oxide epitaxial wafer; respectively removing the gallium oxide cap layer corresponding to a source region of the gallium oxide epitaxial wafer and the gallium oxide cap layer corresponding to a drain region of the gallium oxide epitaxial wafer; respectively doping a portion of the gallium oxide channel layer corresponding to the source region and a portion of the gallium oxide channel layer corresponding to the drain region with an N-type impurity; respectively capping an upper surface of the gallium oxide channel layer corresponding to the source region and an upper surface of the gallium oxide channel layer corresponding to the drain region with a first metal layer to respectively form a source and a drain; and forming a gate.