Patents by Inventor Xiying Costa
Xiying Costa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9142304Abstract: An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate-induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.Type: GrantFiled: February 25, 2015Date of Patent: September 22, 2015Assignee: SanDisk Technologies Inc.Inventors: Xiying Costa, Haibo Li, Masaaki Higashitani, Man L Mui
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Patent number: 9136022Abstract: Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line in a low risk layer so that the risk of both being bad is low.Type: GrantFiled: May 22, 2014Date of Patent: September 15, 2015Assignee: SanDisk Technologies Inc.Inventors: Deepak Raghu, Gautam A. Dusija, Chris Avila, Yingda Dong, Man Mui, Xiying Costa, Pao-Ling Koh
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Patent number: 9099202Abstract: Programming NAND strings in a 3D stacked storage device to a conductive state. Storage elements may be erased by raising their Vt and programmed by lowering their Vt. Programming may include applying a series of increasing voltages to selected bit lines until the selected memory cell is programmed. Unselected bit lines may be held at about ground, or close to ground. The selected word line may be grounded, or be held close to ground. Unselected word lines between the selected word line and the bit line may receive about the selected bit line voltage. Unselected word lines between the source line and the selected word line may receive about half the selected bit line voltage. Programming may be achieved without boosting channels of unselected NAND strings to inhibit them from programming. Therefore, program disturb associated with leakage of boosted channel potential may be avoided.Type: GrantFiled: November 6, 2012Date of Patent: August 4, 2015Assignee: SanDisk Technologies Inc.Inventors: Andrei Mihnea, Xiying Costa, Yanli Zhang
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Publication number: 20150170748Abstract: An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate-induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.Type: ApplicationFiled: February 25, 2015Publication date: June 18, 2015Applicant: SANDISK TECHNOLOGIES INC.Inventors: Xiying Costa, Haibo Li, Masaaki Higashitani, Man L. Mui
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Patent number: 9047973Abstract: An erase operation for a 3D stacked memory device assigned storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.Type: GrantFiled: May 9, 2014Date of Patent: June 2, 2015Assignee: SanDisk Technologies Inc.Inventors: Xiying Costa, Alex Mak, Johann Alsmeier, Man L Mui
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Publication number: 20150117099Abstract: Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line in a low risk layer so that the risk of both being bad is low.Type: ApplicationFiled: May 22, 2014Publication date: April 30, 2015Applicant: SanDisk Technologies Inc.Inventors: Deepak Raghu, Gautam A. Dusija, Chris Avila, Yingda Dong, Man Mui, Xiying Costa, Pao-Ling Koh
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Publication number: 20150121157Abstract: Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line in a low risk layer so that the risk of both being bad is low.Type: ApplicationFiled: October 28, 2013Publication date: April 30, 2015Applicant: SanDisk Technologies Inc.Inventors: Deepak Raghu, Gautam A. Dusija, Chris Avila, Yingda Dong, Man Mui, Xiying Costa, Pao-Ling Koh
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Patent number: 9019775Abstract: An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate-induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.Type: GrantFiled: April 18, 2012Date of Patent: April 28, 2015Assignee: SanDisk Technologies Inc.Inventors: Xiying Costa, Haibo Li, Masaaki Higashitani, Man L Mui
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Publication number: 20150092493Abstract: A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode.Type: ApplicationFiled: December 8, 2014Publication date: April 2, 2015Applicant: SanDisk Technologies Inc.Inventors: Xiying Costa, Alexander Kwok-Tung Mak, Chris Avila, Gautam Dusija, Man Mui
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Publication number: 20150043278Abstract: An erase operation for a 3D stacked memory device assigns storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.Type: ApplicationFiled: October 27, 2014Publication date: February 12, 2015Applicant: SANDISK TECHNOLOGIES INC.Inventors: Xiying Costa, Alex Mak, Johann Alsmeier, Man L. Mui
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Publication number: 20150037950Abstract: A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates.Type: ApplicationFiled: October 17, 2014Publication date: February 5, 2015Inventors: Johann Alsmeier, Raghuveer S. Makala, Xiying Costa, Yanli Zhang
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Patent number: 8934292Abstract: Improved methods for programming multi-level metal oxide memory cells balance applied voltage and current to provide improved performance. Set programming, which transitions the memory cell to a lower resistance state, is accomplished by determining an appropriate programming voltage and current limit for the objective resistance state to be achieved in the programming and then applying a pulse having the determined set electrical characteristics. Reset programming, which transitions the memory cell to a higher resistance state, is accomplished by determining an appropriate programming voltage and optionally current limit for the state to be achieved in the programming and then applying a pulse having the determined electrical characteristics. The algorithm used to determine the appropriate set or reset programming voltage and current values provides for effective programming without stressing the memory element.Type: GrantFiled: March 18, 2011Date of Patent: January 13, 2015Assignee: SanDisk 3D LLCInventors: Xiying Costa, Yibo Nian, Roy Scheuerlein, Tz-Yi Liu, Chandrasekhar Reddy Gorla
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Patent number: 8923054Abstract: A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode.Type: GrantFiled: January 10, 2014Date of Patent: December 30, 2014Assignee: SanDisk Technologies Inc.Inventors: Xiying Costa, Alexander Kwog-Tung Mak, Chris Avila, Gautam Dusija, Man Mui
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Publication number: 20140369122Abstract: A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode.Type: ApplicationFiled: January 10, 2014Publication date: December 18, 2014Applicant: SanDisk Technologies Inc.Inventors: Xiying Costa, Alexander Kwok-Tung Mak, Chris Avila, Gautam Dusija, Man Mui
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Publication number: 20140369123Abstract: A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode.Type: ApplicationFiled: May 9, 2014Publication date: December 18, 2014Applicant: SanDisk Technologies Inc.Inventors: Xiying Costa, Alexander Kwok-Tung Mak, Chris Avila, Gautam Dusija, Man Mui
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Patent number: 8913431Abstract: A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode.Type: GrantFiled: May 9, 2014Date of Patent: December 16, 2014Assignee: SanDisk Technologies Inc.Inventors: Xiying Costa, Alexander Kwok-Tung Mak, Chris Avila, Gautam Dusija, Man Mui
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Patent number: 8908444Abstract: An erase operation for a 3D stacked memory device adjusts a start time of an erase period and/or a duration of the erase period for each storage element based on a position of the storage element. A voltage is applied to one or both drive ends of a NAND string to pre-charge a channel to a level which is sufficient to create gate-induced drain leakage at the select gate transistors. With timing based on a storage element's distance from the driven end, the control gate voltage is lowered to encourage tunneling of holes into a charge trapping layer in the erase period. The lowered control gate voltage results in a channel-to-control gate voltage which is sufficiently high to encourage tunneling. The duration of the erase period is also increased when the distance from the driven end is greater. As a result, a narrow erase distribution can be achieved.Type: GrantFiled: August 6, 2013Date of Patent: December 9, 2014Assignee: SanDisk Technologies Inc.Inventors: Xiying Costa, Seung Yu, Roy E. Scheuerlein, Haibo Li, Man L. Mui
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Patent number: 8908435Abstract: An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line. A more consistent gate-induced drain leakage (GIDL) at the select gates can be generated to charge up the body of the NAND string. Further, the select gate voltage can be stepped up with the erase voltage to avoid an excessive drain-to-gate voltage across the select gates which causes degradation. The step up in the select gate voltage can begin with the first erase-verify iteration of an erase operation, or at a predetermined or adaptively determined erase-verify iteration, such as based on a number of program-erase cycles.Type: GrantFiled: December 21, 2011Date of Patent: December 9, 2014Assignee: SanDisk Technologies Inc.Inventors: Haibo Li, Xiying Costa, Chenfeng Zhang
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Patent number: 8885412Abstract: An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line. A more consistent gate-induced drain leakage (GIDL) at the select gates can be generated to charge up the body of the NAND string. Further, the select gate voltage can be stepped up with the erase voltage to avoid an excessive drain-to-gate voltage across the select gates which causes degradation. The step up in the select gate voltage can begin with the first erase-verify iteration of an erase operation, or at a predetermined or adaptively determined erase-verify iteration, such as based on a number of program-erase cycles.Type: GrantFiled: April 16, 2014Date of Patent: November 11, 2014Assignee: SanDisk Technologies Inc.Inventors: Haibo Li, Xiying Costa, Chenfeng Zhang
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Patent number: 8883589Abstract: A method of forming a memory cell is provided, the method including forming a diode including a first region having a first conductivity type, counter-doping the diode to change the first region to a second conductivity type, and forming a memory element coupled in series with the diode. Other aspects are also provided.Type: GrantFiled: September 28, 2010Date of Patent: November 11, 2014Assignee: SanDisk 3D LLCInventors: Xiying Costa, Abhijit Bandyopadhyay, Kun Hou, Brian Le, Yung-Tin Chen